How to porting u-boot to my own board?

Hi LiangYi,

> Have you ever seen this problem?

No, sorry ... I'm not familiar with that error.

I rarely use the IDE ... if there is a setting so you can see how the flash programmer is

invoked by the IDE (and parameters) perhaps that will resolve your

issue.

Regards,

--Scott

Hi Scott,

Sorry for so many questions. Because I have never used u-boot(cygwin or linux) before, so I have many questions. Now, I am being in confused about u-boot.

I want to re-new my mind now in order to make u-boot work on my board.

> First, I want to ask you the relation between u-boot, flash, sdram and epcs4.

> Furthermore, where are various kinds of files(uImage, .bin, .sof, .flash, .srec and so on) run or properly

stored in for u-boot? Is u-boot stored in flash or EPCS?

> Finally, what procedure should I follow and test step by step in order to achieve u-boot, boot uClinux on

my board?

Thank you,

LiangYi

Hi LiangYi,

> > First, I want to ask you the relation between u-boot, flash, sdram and epcs4.

u-boot is an application (a boot monitor) that can be stored in flash or an epcs device.

When the cpu is reset, u-boot is copied to sdram by: itself (if it is stored at the reset address);

or the epcs controller boot code.

> > Furthermore, where are various kinds of files(uImage, .bin, .sof, .flash, .srec and so on) run

> or properly stored in for u-boot?

uimage or an "img" file is most commonly used to store a kernel binary (but it can be used

to store data, ram disk images, scripts, etc.). The kernel image can be compressed. It can be stored

anywhere you want. In flash, in ram (downloaded by u-boot via serial port, TFTP or NFS), in an epcs

device (if the device is large enough). An image file is nothing more than a small header prepended

to your original file. The header contains information about the binary data that follows and includes

a 32-bit CRC for the data, and a 32-bit CRC for the header itself.

u-boot.bin is simply the u-boot .text, .data, .rodata, etc. u-boot.srec is an S-record file for

u-boot ... it's just a convenience for use with EPROM programmers, etc. The flash file is used by

nios2-flash-programmer (it just happens to in S-record format).

> Is u-boot stored in flash or EPCS?

Either ... that's up to you.

> > Finally, what procedure should I follow and test step by step in order to achieve u-boot,

> boot uClinux on my board?

Create an image file for uClinux, load it onto your board, then execute the u-boot "bootm"

command (this is all in the u-boot README).

Regards,

--Scott

Congratulations to Scott, you are nios god plus

Hi,

I have received the staff from Scott about U-boot on NiosII. Thank you, Scott. I am going to test it on my custom board, on which there are EP1C6, 16MB flash, 16MB SDRAM, Ethernet. "both of us can share our success."

Hi Scott,

I retry run u-boot in epcs4 and it successed.

Reset Address: epcs_controller, base address=0x00400000.

Exception Address: sdram, 8M, base address=0x01000000.

Am29DL323GB Flash: 4M, base address:=0x00000000.

Here is the information in hyper-terminal

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

U-Boot 1.1.3 (Sep 26 2005 - 22:44:56)

CPU : Nios-II

SYSID : 8a712a61, Mon Sep 26 12:41:05 2005

BOARD : Microtronix Cyclone 1C20 Kit

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode

WARNING: flash_make_cmd: unsuppported LittleEndian mode# # Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB

*** Warning - bad CRC, using default environment

==>[/b]

--- Quote End ---

So, I have some question to ask you.

1. WARNING: flash_make_cmd: unsuppported LittleEndian mode

# # Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB

I do not know what is the reason and how to correct. I use cfi_flash.c you send to me.

2. I do it as you replied to DW. But I still have questions.

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

1. Create the u-boot flash file with elf2flash and these parameters:

$ elf2flash --epcs --base=0x0 --end=0x7fffffff --flash=U15 --input=u-boot --output=u-boot.flash --boot=boot_loader_epcs.srec[/b]

--- Quote End ---

Here, --base is epcs base or cfi flash base. If it is cfi flash, why --end=0x7fffffff.

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

2. Download u-boot to the epcs device.

$ nios2-flash-programmer --epcs --input=u-boot.flash --sof=<path to pgm sof>

3. Create the configuration flash file.

$ sof2flash --epcs --input=<path to your system sof> --offset=0x0 --output=config.flash

4. Download the configuration flash file to the epcs device.

$ nios2-flash-programmer --epcs --input=config.flash --sof=<path to pgm sof> --relocate[/b]

--- Quote End ---

Here, what address the u-boot.flash download to?

I have read nios-flash-programmer-guide. In Booting From EPCS Serial Configuration Devices part, it says The flash programmer first checks the size of the FPGA configuration data, then appends the software content to the end of it in the EPCS device. Is flash-programmer can know to distribute the address space of configuration data and u-boot.flash intelligently?

--relocate: relocate code following a sof <epcs mode only>. Are all data address in epcs distributed by --relocate parameter, and --relocate is only used in programming fpga config data to epcs?

The data in epcs are in the sequence below,

.sof ----- 0x0

boot_loader_srec(or store in on-chip rom),

u-boot

When run, u-boot is relocated by boot_loader_srec to run in sdram text_base.

Right?

Thank you,

LiangYi

Hi LiangYi,

> Am29DL323GB Flash: 4M, base address:=0x00000000.

Is your base address correct? The base address for your flash was 0x0020_0000 in the last

email you sent.

> *** Warning - bad CRC, using default environment

-#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)

+#define CFG_ENV_ADDR CFG_FLASH_BASE /* Or whatever you like */

Since the reset address has changed to the epcs controller, the vanilla CFG_ENV_ADDR is not

valid -- the default configs for the altera boards assume the reset address is in flash ... and

assume the environment is stored in the sector following the u-boot binary.

> Here, --base is epcs base or cfi flash base. If it is cfi flash, why --end=0x7fffffff.

It&#39;s just a simple way to grab everything from the elf file since the Nios II memory space is

only 2GB [0000_0000 - 7fff_ffff]. The flash file for an epcs is handled a bit different -- it

contains a sequence of length-address-data records that must be copied to the appropriate

address in the Nios II memory space. These records are actually programmed into the

epcs. For a parallel (CFI) flash device, only the data is programmed into the device (if it falls

within the device&#39;s address range).

> Is flash-programmer can know to allot the address space to configuration data and

> u-boot.flash intelligently?

Yes, otherwise you would overwrite your FPGA configuration data.

> The data in epcs are in the sequence, .sof, boot_loader_srec(or store in on-chip rom), u-boot,

> then u-boot is relocated by boot_loader_srec to run in sdram text_base.

> Right?

Yes (the onchip rom is part of the sof). You can examine all of this using the u-boot epcs commands:

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

==> help epcs

epcs

epcs erase start [end]

- erase sector start or sectors start through end.

epcs info

- display EPCS device information.

epcs protect on | off

- turn device protection on or off.

epcs read addr offset count

- read count bytes from offset to addr.

epcs write addr offset count

- write count bytes to offset from addr.

epcs verify addr offset count

- verify count bytes at offset from addr.

==> epcs info

EPCS4 : 512 kbytes (8 sectors x 64 kbytes, 256 bytes/page)

status: 0x00 (WIP:0, WEL:0, PROT:off)

config: 0x02d453 (185427) bytes

0: 000000 data @ 0x000010

1: 010000 data @ 0x010000

2: 020000 data @ 0x020000

3: 030000 data @ 0x030000

4: 040000 data @ 0x040000

5: 050000 erased

6: 060000 erased

7: 070000 erased

==> epcs read 400 2d453 10

epcs: read 00000400 <- 02d453 (0x10 bytes)

==> md.b 400 10

00000400: c2 2d 80 00 00 00 bf 00 28 10 00 80 2c 00 02 80 .-......(...,...[/b]

--- Quote End ---

If you bit reverse the first two words you get: 0001_b443 00fc_0000

which is in fact, the length and address of the .text section for my particular board.

Regards,

--Scott

Hi Scott,

When programming epcs device as above, is --relocate parameter only used in the last one nios2-flash-programmer command? Whatever contents which is programmed in epcs last.

LiangYi

Hi Scott,

>>>

I see a text in PK1C20.h.

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

/*------------------------------------------------------------------------

* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for

* epcs device access is enabled. The base address is the epcs

* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.

* The register base is currently at offset 0x600 from the memory base.

*----------------------------------------------------------------------*/# define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */[/b]

--- Quote End ---

I look the epcs controller data sheet, its registers map is

0x000

. Boot ROM Memory

0x0FF

0x100 Read Data

0x101 Write Data

0x102 Status

0x103 Control

0x104 Reserved

0x105 Slave Enable

0x106 End of Packet

Why the text says <div class='quotetop'>QUOTE </div>

--- Quote Start ---

"The register base is currently at offset 0x600 from the memory base."[/b]

--- Quote End ---

I try to set offset=0x110,# define CFG_NIOS_EPCSBASE 0x00400110(my epcs base=0x00400000).

When run ==>epcs info, it display

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

==> epcs info

epcs: device not found.

==>[/b]

--- Quote End ---

Why, I have avoided the epcs registers address! I retry offset=0x200, it runs OK.

Another,

0x000

. Boot ROM Memory

0x0FF

Does here store the boot_loader_epcs.srec? And the boot_loader_epcs.srec runs in FPGA on-chip-rom?

I do not know it clearly, and altera&#39;s document do not describe this.

>>>

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

> Am29DL323GB Flash: 4M, base address:=0x00000000.

Is your base address correct? The base address for your flash was 0x0020_0000 in the last

email you sent.[/b]

--- Quote End ---

Yes, my flash base is 0x0.

>>>

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

> *** Warning - bad CRC, using default environment

-#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)

+#define CFG_ENV_ADDR CFG_FLASH_BASE /* Or whatever you like */[/b]

--- Quote End ---

I change as you say, but have no effect on u-boot boot-up message.

>>>

I think the sequence of u-boot running in epcs4 is:

First, the FPGA is configured with config data in epcs.

Then, boot_loader_epcs.srec stored in epcs runs in FPGA on-chip rom and copy u-boot to the u-boot TEXT_BASE(elf link address).

Finally, u-boot runs in TEXT_BASE, initial hardware and generate the environment(heap, global data, stack).

Right?

Thank you,

LiangYi

Hi LiangYi,

> When programming epcs device as above, is --relocate parameter only used in the last

> one nios2-flash-programmer command?

The documentation for the --relocate option is vague. The user guide does not even mention it,

and the --help option only states:<div class='quotetop'>QUOTE </div>

--- Quote Start ---

The --relocate option is used with EPCS serial configuration devices. If data has already been programmed into the EPCS device, it will be relocated at a higher address to make room for the new data being programmed.[/b]

--- Quote End ---

However, my observations and some script hacking indicate that only non-configuration data is actually

relocated. Since the application (u-boot) data is programmed immediately after the configuration data,

it needs to be relocated when you write new FPGA configuration data (sof) to the the epcs device (to

account for changes in the size of the sof data).

Basically, I use the --relocate parameter only when programming a new sof to the epcs -- and I have

never had a problem -- the existing u-boot data in the epcs is always where it needs to be :-)

> Why the text says

> QUOTE

> "The register base is currently at offset 0x600 from the memory base."

An "epcs controller" is simply ASMI + on chip memory + boot code. The on chip memory that contains

the boot code comes first (lower addresses) and the ASMI registers follow. The last I checked, the

size of the epcs on chip memory is 512 bytes (0x200) ... so the offset of the ASMI registers should

be 0x200. Perhaps this bug just got lucky with some address bus aliasing ;-)

> I try to set offset=0x110,# define CFG_NIOS_EPCSBASE 0x00400110(my epcs base=0x00400000).

If you&#39;re using Nios II 5.0, don&#39;t do that. An offset of 0x200 should be correct -- try it ;-)

> When run ==>epcs info, it display

> QUOTE

> ==> epcs info

> epcs: device not found.

Correct -- it did not find the device because the offset is not correct.

> I retry offset=0x200, it runs OK.

Yep ... as above.

> I change as you say, but have no effect on u-boot boot-up message.

Until you can successfully write your environment to flash you will get the warning message.

Also, I tried the cfi_flash.c that I sent you on two different boards (EP1C20 and PCI-5441) and

it works ok for me. However, both boards use 8-bit devices and do not implement data cache.

If you have a data cache, I don&#39;t think cfi_flash.c will work -- it&#39;s currently not coded to use

the ld/st io instructions.

Regards,

--Scott

Hi Scott,

Now I am well-known about u-boot start-up from epcs device.

<1> FPGA is configured with config data in epcs first.

<2> Then, boot_loader_epcs.srec stored in epcs runs in FPGA on-chip rom and copy u-boot to the u-boot

TEXT_BASE(elf link address).

<3> Finally, u-boot runs in TEXT_BASE(here is in sdram 0x017C_0000, the last 256KB. My sdram is 8M, base=0x0100_0000), generate the environment(heap, global data, stack) and initial hardware for use.

Right?

My timer, epcs, led, uart and sysid are initialized ok, now.

Next, I &#39;ll try to make my flash work.

LiangYi