How to porting u-boot to my own board?

Hi Scott,

>>>

I see a text in PK1C20.h.

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

/*------------------------------------------------------------------------

* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for

* epcs device access is enabled. The base address is the epcs

* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.

* The register base is currently at offset 0x600 from the memory base.

*----------------------------------------------------------------------*/# define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */[/b]

--- Quote End ---

I look the epcs controller data sheet, its registers map is

0x000

. Boot ROM Memory

0x0FF

0x100 Read Data

0x101 Write Data

0x102 Status

0x103 Control

0x104 Reserved

0x105 Slave Enable

0x106 End of Packet

Why the text says <div class='quotetop'>QUOTE </div>

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"The register base is currently at offset 0x600 from the memory base."[/b]

--- Quote End ---

I try to set offset=0x110,# define CFG_NIOS_EPCSBASE 0x00400110(my epcs base=0x00400000).

When run ==>epcs info, it display

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==> epcs info

epcs: device not found.

==>[/b]

--- Quote End ---

Why, I have avoided the epcs registers address! I retry offset=0x200, it runs OK.

Another,

0x000

. Boot ROM Memory

0x0FF

Does here store the boot_loader_epcs.srec? And the boot_loader_epcs.srec runs in FPGA on-chip-rom?

I do not know it clearly, and altera&#39;s document do not describe this.

>>>

<div class='quotetop'>QUOTE </div>

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> Am29DL323GB Flash: 4M, base address:=0x00000000.

Is your base address correct? The base address for your flash was 0x0020_0000 in the last

email you sent.[/b]

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Yes, my flash base is 0x0.

>>>

<div class='quotetop'>QUOTE </div>

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> *** Warning - bad CRC, using default environment

-#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)

+#define CFG_ENV_ADDR CFG_FLASH_BASE /* Or whatever you like */[/b]

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I change as you say, but have no effect on u-boot boot-up message.

>>>

I think the sequence of u-boot running in epcs4 is:

First, the FPGA is configured with config data in epcs.

Then, boot_loader_epcs.srec stored in epcs runs in FPGA on-chip rom and copy u-boot to the u-boot TEXT_BASE(elf link address).

Finally, u-boot runs in TEXT_BASE, initial hardware and generate the environment(heap, global data, stack).

Right?

Thank you,

LiangYi