Honored ContributorI use IUL in SOPC to add a memory slave peripheral.I add 18 address line (add[17..0]) and then
in the Quartus it appears add[19..0], I read the datasheet of AvalonBus about Dynamic bus sizing. But I did't understand it.Did I leave the add[0] and add[1] blank or something? Thanks a lot.http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif
Honored Contributorwhich version of quartus and Nios are you using ?
what are your settings of user logic in sopc builder (mainly databus width ?)? with dynamic bus sizing: 8 Bit Databus : connect A0..Ax of RAM to A0..Ax of NIOS ADDRESS BUSS 16 Bit Databus : connect A0..Ax of RAM to A1..A(x+1) of NIOS ADDRESS BUSS 32 Bit Databus : connect A0..Ax of RAM to A2..A(x+2) of NIOS ADDRESS BUSS in case of 16 Bit Databus leave A0 of NIOS ADRESS BUS unconnected in case of 32 Bit Databus leave A0+A1 of NIOS ADRESS BUS unconnected REMARK: Altera told me that there was a change in the addressing scheme with NIOS 1.1 for native slaves. Table 15 Page 100 of Avalon Bus Specification should be corrected as following: Alignment | Master Width | Slave Width | A[0] of Slave is connected to Byte Address Bit Number native | 32 | 32 | A2(NIOS1.0) A2(NIOS1.1) native | 32 | 16 | A2(NIOS1.0) A1(NIOS1.1) native | 32 | 8 | A2(NIOS1.0) A0(NIOS1.1) dynamic | 32 | 32 | A2 dynamic | 32 | 16 | A1 dynamic | 32 | 8 | A0 PLEASE correct me if i tell something wrong!Honored ContributorIf your peripheral has a native data width between 17 and 32 bits then this sounds correct (would want to access 4 bytes at a time so A[0] and A[1] are not needed).
Fischer the change you are referring to appears in SOPC Builder 4.2 and up. It was specific to native tri-state slaves (in short before 4.2 they did not behave the way you describbed and now they do). If you can describe your peripheral and the bus it is connected to we can give you a better answer.
