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Altera_Forum's avatar
Altera_Forum
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14 years ago

Hot FPGA after design upload

Hello,

I've developed a board with EP3C40F324 FPGA which includes National Ethernet PHY and two separate DDR memory chips connected to banks (3,4) and (7,8). These particular banks are powered 2.5V and VRef pins of those banks are powered 1.25V. Other banks are powered 3.3V

The problem:

When I upload a simple design, the design works fine, but when I add DDR memory controller (either both chips, or one chip), the FPGA gets hot (I can't keep finger on it) in about 20-30 seconds. Memory doesn't work, although the clock is working fine, as the whole other logic.

Memory pins are terminated 22ohm in series and 56ohm in parallel, since I've run out of pins and RDUP, RDN pins had to be used for other purposes and left as IOs.

I've probably made a mistake by saving money and using simple resistor divider to generate 1.25V from 2.5V, but even if I disconnect the VRef powering - nothing changes.

I believe PLL instantiated by memory controller is working fine, since I see the correct clock going out the FPGA pins.

I've made no workarounds connecting pins to FPGA. I've developed a design and a board in parallel to check if my memory chip is connected correctly to DQ and DQS pins in FPGA. Then, I've used a TCL script generated by memory controller to set up all the pins in the design, so I get no errors when compiling a design.

I suppose I get a high current flow through FPGA, which makes it hot. Which part of the memory interface pins could cause that?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I wonder, how you're terminating the RAM signals without a 1.25V supply?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well, doing that test, I've removed parallel termination resistors (56ohm) and disconnected the 1.25V supply.

    According to DDR specs, parallel termination must be used only if wire length on the board is >2 inches (>5cm). The longest wire on my board doesn't reach 1 inch limit, so I am within specs with that test.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    According to DDR specs, parallel termination must be used only if wire length on the board is >2 inches (>5cm). The longest wire on my board doesn't reach 1 inch limit, so I am within specs with that test.

    --- Quote End ---

    You still need to make sure the voltage swing of your signals is still within spec, even if you have designed the board without a DDR termination voltage.

    I did the same on my PowerPC board, but the voltage analysis with Hyperlynx showed that the voltage swing violated specification. The solution was to program the DDR memory to drive at half-strength, and the controller to drive at half-strength.

    I'm not sure that using the wrong drive strength would cause your FPGA to get hot though ... but its worth looking at. The DDR drive strength can be changed as part of the setup words. I forget the details, but its in the Micron DDR data sheet somewhere, here's a section of my BDI2000 debugger initialization for the PowerPC ... 

    
; DDR mode configuration (p9-24 )
; ----------------------
; DDR_SDRAM_MODE
;   ESDMODE  Extended SDRAM mode
;   SDMODE   SDRAM mode
;
; The mode settings are defined by the DDR memory manufacturer.
; The CARMA board uses 5 pieces of 16-bit wide DDR1 .
; The bus is 64-bit plus ECC (plus one unused byte).
; The DDR bus is not terminated, and the controller and
; devices must use half-strength mode.
;
; SDMODE
;  OM  =   0  normal operating mode
;   CL  = 010  CAS latency of 2
;     BT  =   0  sequential burst
;   BL  = 010  burst-length of 4
;
;   SDMODE = 0000_0000_0010_0010b = 0022b
;
; ESDMODE
;  OM  =  0  operating mode
;     DS  =  1  reduced drive strength
;     DLL =  0  enabled
;
;  ESDMODE = 0000_0000_0000_0010b = 0002h
;
; The ESDMODE2 and ESDMODE3 registers are set to zero.
;
WM32    0xE0002118      0x00020022      ;DDR_SDRAM_MODE
WM32    0xE000211C      0x00000000      ;DDR_SDRAM_MODE_2

    The drive strength for the DDR is in the ESDMODE register.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    To explain the excessive power dissipation I would rather expect a more basic problem like shorted FPGA outputs. Series termination resistors should allow to probe the signals and check if all memory related signals are assigned and wired correctly.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yep, I also expect some tristate to be fault or output to be connected to certain net. Probably I'll go for pin checking one-by-one.