Altera_Forum
Honored Contributor
Honored ContributorHot FPGA after design upload
Hello,
I've developed a board with EP3C40F324 FPGA which includes National Ethernet PHY and two separate DDR memory chips connected to banks (3,4) and (7,8). These particular banks are powered 2.5V and VRef pins of those banks are powered 1.25V. Other banks are powered 3.3V The problem: When I upload a simple design, the design works fine, but when I add DDR memory controller (either both chips, or one chip), the FPGA gets hot (I can't keep finger on it) in about 20-30 seconds. Memory doesn't work, although the clock is working fine, as the whole other logic. Memory pins are terminated 22ohm in series and 56ohm in parallel, since I've run out of pins and RDUP, RDN pins had to be used for other purposes and left as IOs. I've probably made a mistake by saving money and using simple resistor divider to generate 1.25V from 2.5V, but even if I disconnect the VRef powering - nothing changes. I believe PLL instantiated by memory controller is working fine, since I see the correct clock going out the FPGA pins. I've made no workarounds connecting pins to FPGA. I've developed a design and a board in parallel to check if my memory chip is connected correctly to DQ and DQS pins in FPGA. Then, I've used a TCL script generated by memory controller to set up all the pins in the design, so I get no errors when compiling a design. I suppose I get a high current flow through FPGA, which makes it hot. Which part of the memory interface pins could cause that?
