Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hot FPGA after design upload

Hello, I've developed a board with EP3C40F324 FPGA which includes National Ethernet PHY and two separate DDR memory chips connected to banks (3,4) and (7,8). These particular banks are powered 2.5...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Well, doing that test, I've removed parallel termination resistors (56ohm) and disconnected the 1.25V supply.

According to DDR specs, parallel termination must be used only if wire length on the board is >2 inches (>5cm). The longest wire on my board doesn't reach 1 inch limit, so I am within specs with that test.