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Altera_Forum
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14 years ago

Hot FPGA after design upload

Hello, I've developed a board with EP3C40F324 FPGA which includes National Ethernet PHY and two separate DDR memory chips connected to banks (3,4) and (7,8). These particular banks are powered 2.5...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yep, I also expect some tristate to be fault or output to be connected to certain net. Probably I'll go for pin checking one-by-one.