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According to DDR specs, parallel termination must be used only if wire length on the board is >2 inches (>5cm). The longest wire on my board doesn't reach 1 inch limit, so I am within specs with that test.
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You still need to make sure the voltage swing of your signals is still within spec, even if you have designed the board without a DDR termination voltage.
I did the same on my PowerPC board, but the voltage analysis with Hyperlynx showed that the voltage swing violated specification. The solution was to program the DDR memory to drive at half-strength, and the controller to drive at half-strength.
I'm not sure that using the wrong drive strength would cause your FPGA to get hot though ... but its worth looking at. The DDR drive strength can be changed as part of the setup words. I forget the details, but its in the Micron DDR data sheet somewhere, here's a section of my BDI2000 debugger initialization for the PowerPC ...
; DDR mode configuration (p9-24 )
; ----------------------
; DDR_SDRAM_MODE
; ESDMODE Extended SDRAM mode
; SDMODE SDRAM mode
;
; The mode settings are defined by the DDR memory manufacturer.
; The CARMA board uses 5 pieces of 16-bit wide DDR1 .
; The bus is 64-bit plus ECC (plus one unused byte).
; The DDR bus is not terminated, and the controller and
; devices must use half-strength mode.
;
; SDMODE
; OM = 0 normal operating mode
; CL = 010 CAS latency of 2
; BT = 0 sequential burst
; BL = 010 burst-length of 4
;
; SDMODE = 0000_0000_0010_0010b = 0022b
;
; ESDMODE
; OM = 0 operating mode
; DS = 1 reduced drive strength
; DLL = 0 enabled
;
; ESDMODE = 0000_0000_0000_0010b = 0002h
;
; The ESDMODE2 and ESDMODE3 registers are set to zero.
;
WM32 0xE0002118 0x00020022 ;DDR_SDRAM_MODE
WM32 0xE000211C 0x00000000 ;DDR_SDRAM_MODE_2
The drive strength for the DDR is in the ESDMODE register.
Cheers,
Dave
Honored Contributor
