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Altera_Forum
Honored Contributor
Honored ContributorHot FPGA after design upload
Hello, I've developed a board with EP3C40F324 FPGA which includes National Ethernet PHY and two separate DDR memory chips connected to banks (3,4) and (7,8). These particular banks are powered 2.5...
Altera_ForumHonored Contributor
Honored ContributorI wonder, how you're terminating the RAM signals without a 1.25V supply?
