Help! "NiosII download failed!"

Now,it can download ,but when verify ,errors appear!

Can anybody help me? Thanks in advance!

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: OK

Reading System ID at address 0x00102098: verified

Downloading 00800020 ( 0%)

Downloading 00810000 (89%)

Downloaded 72KB in 0.9s (80.0KB/s)

Verifying 00800020 ( 0%)

Verify failed between address 0x800020 and 0x80FFFF

Leaving target processor paused

But I build a new nios-cpu ,it works well.

The errors didn't occur again,but I still don't kown the reason wky the first one did not work !

Could anyone help me?

--- Quote Start ---

originally posted by wallace@Jul 21 2006, 08:14 AM

but i build a new nios-cpu ,it works well.

the errors didn't occur again,but i still don't kown the reason wky the first one did not work !

could anyone help me?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17052)

--- quote end ---

--- Quote End ---

Hi i&#39;m getting started now with a stratix II (EP2S60F1020C4) and i had the same problem :

Verifying 03000020 ( 0%)

Verify failed

Leaving target processor paused.

I solved it by downloading an the board the standard.qpf file that i found i the directory:

altera\kits\StratixII_DSP_Kit-v1.1.0\Examples\HW\NiosII\example_designs\vhdl\standard

I have downloaded this file without compiling it.

I started Nios II IDE and runned a sample project unchecking Validate Nios II System ID before software downolad.

Everything works fine now.Good Luck and sorry if said uncorrect things but i&#39;m not so expert as you are! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

--- Quote Start ---

originally posted by buca+jul 25 2006, 12:50 am--><div class='quotetop'>quote (buca @ jul 25 2006, 12:50 am)</div>

--- quote start ---

<!--quotebegin-wallace@Jul 21 2006, 08:14 AM

but i build a new nios-cpu ,it works well.

the errors didn&#39;t occur again,but i still don&#39;t kown the reason wky the first one did not work !

could anyone help me?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17052)

--- quote end ---

--- Quote End ---

Hi i&#39;m getting started now with a stratix II (EP2S60F1020C4) and i had the same problem :

Verifying 03000020 ( 0%)

Verify failed

Leaving target processor paused.

I solved it by downloading an the board the standard.qpf file that i found i the directory:

altera\kits\StratixII_DSP_Kit-v1.1.0\Examples\HW\NiosII\example_designs\vhdl\standard

I have downloaded this file without compiling it.

I started Nios II IDE and runned a sample project unchecking Validate Nios II System ID before software downolad.

Everything works fine now.Good Luck and sorry if said uncorrect things but i&#39;m not so expert as you are! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17073)</div>

[/b]

--- Quote End ---

Hello!

but I must download the system which I bulid according my requires.Is there something that I haven&#39;t paied attention to?

--- Quote Start ---

originally posted by wallace@Jul 19 2006, 06:20 AM

now,it can download ,but when verify ,errors appear!

can anybody help me? thanks in advance!

using cable "usb-blaster [usb-0]", device 1, instance 0x00

pausing target processor: ok

reading system id at address 0x00102098: verified

downloading 00800020 ( 0%)

downloading 00810000 (89%)

downloaded 72kb in 0.9s (80.0kb/s)

verifying 00800020 ( 0%)

verify failed between address 0x800020 and 0x80ffff

leaving target processor paused

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17007)

--- quote end ---

--- Quote End ---

There are so many reasons for the Verify fail, that is why it is so popular.

Here are a few that I have seen

1. Bad memory interface, physical board problem

2. Timing issue with memory

3. Lack of non-volatile memory. This confuses processor.

If you have problems with downloading programs from the IDE, I suggest to try reconfigure your FPGA with a "simple" test design that is a sub-set of your design. For example to isolate if your problem is SDRAM or SRAM, try to use/add onchip_memory to run hello world from. If the onchip_memory program runs, but loading the program to SDRAM/sram still fails, I would take a closer look at the memory timing or phase setting.

I am using the DE2 board.

I faced the same problem if I instantiated the cpu in VHDL.

However , it work fine if I instantiated the cpu in Verilog.

Why is it so???? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif