Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Fail to restart program after poweroff and poweron

Best wishes and happy new year for all!!

I have a problem on rebooting my project.

The program runs ok when flashed on my nios ii system board (is a custom board consist of an cyclone ii fpga, sdram, epcs flash device and an lcd), but when I power off and then power on the board the program does not start any more!

I use an EPCS4 4Mbit flash connected to my NIOS II.

On SOPC builder I put 0x0 as starting address of my EPCS4 flash device connected and the reset vector on cpu also to starts on 0x0 and the exception vector is on sdram with offset 0x20.

I flashed the system and the program (sof and elf files) using flash programmer from Eclipse Ganymede menu!

I do not know if that is enough or have to do more actions?

Do I have to add more files? (.pof for example)?

Can you please help ?

Thanks in advance!

20 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You're first step is to verify that the FPGA is indeed getting programmed. Once you determine that to be true, you can move on to finding out if something is wrong on the software side of things.

    Is the FPGA getting programmed?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thank you for your reply!

    Iwould like to find out if the fpga is getting programmed ob power on but I do not know how to do! Any sugestions?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    One simple way for you would be to cycle power on the board, then try and download and run your software on the NIOS. If the NIOS isn't there (because the FPGA never got configured), then you'll get an error message indicating that no NIOS processors were detected.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    If I cycle power on the board I must use Quartus II Programmer to flash .sof file. But as soon as programmer finishes the software starts run immediately !!

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Well it sounds like your software is loaded into the flash but either:

    1 - The FPGA programming file is not programmed into the flash.

    2 - Something is failing in the configuration.

    Are the MSEL pins on the FPGA correctly set for Active Serial Programming?

    http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf

    If you have an oscilloscope handy you might want to start probing the config pins to see what is happening there.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I expect case 1, because you mentioned to have only programmed a sof version of the FPGA configuaration. It's volatile. The configuration must go to the EPCS4 as well.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I think he's using the NIOS II flash programmer to program the EPCS device. You give it the SOF file and it does the conversion for you.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thank you all for you participation!

    I used the nios ii console and tried to start the script generated by the nios flash programmer.

    After the script finished I see that the message in the last lines is that...

    ........

    Device size is 512KByte <4Mbit>

    erase regions are:

    offset 0: 8 x 64K

    EPCS status is 0x00

    Input file is too large to fit <device size =0x80000>

    -----------------------------------------------

    I suppose I must find a way to minimize my program...

    .. I enabled the small C library and started again the script but the result is the same!

    Any suggestions?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Well it seems like we previously determined that your software program is indeed being programmed into the flash. Are you sure it's not claiming that the FPGA configuration file is too large rather than your software image?

    It may be that you will only be able to fit your FPGA image into the EPCS4 device. And you may need to enable compression to accomplish this.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I followed the procedure and I have generated a compressed .pof file but the result is the same.

    I am not sure if I do the procedure of flashing in the right way!

    Is there any quick tutorial on flashing?

    I have already ordered a bigger flash EPCS64 chip and I am waiting to arrive but till then I must be sure that I am not doing something wrong on the flashing procedure!