Altera_Forum
Honored Contributor
15 years agoEthernet problem turned out to be a memory / DMA problem
So I have spent a couple weeks trying to troubleshoot Ethernet functionality on my custom board. I finally isolated the problem last night. Ethernet data is getting into the FPGA just fine. I can compare Signaltap data of the MII bus inputs to Wireshark data and they match perfectly. But when I dump the packet contents from RAM, they are garbage. So it appears that the SGDMA controllers are not playing nice with my SDRAM.
The interesting thing is my CPU can access RAM just fine without a hiccup. When I run the memory tester in the Eclipse tools, every bit passes. When I run Linux, the kernel is stable as a rock and code does not seem to ever crash. But ethernet data into the system is beautiful in Signaltap but garbage in RAM. The interesting thing is I get the same behavior in Linux and Eclipse / Micrium / HAL. The TSE can negotiate a connection with the PHY just fine but packets are silently dropped because they are garbage. So I am guessing I probably have my RAM timing numbers off. I am not using a RAM chip explicity supported in NIOS. I am using a Micron MT48LC16MA2. How would you troubleshoot this problem? David. Do I need to put a scope on the memory pins? All I know for sure is that Ethernet data is getting into the FPGA intact but not making it into SDRAM intact.