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Altera_Forum's avatar
Altera_Forum
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15 years ago

Error: Downloading elf file. Problems with SDRAM?

Hi!

I've got some trouble with the NIOS II IDE. I've build a SOPC Builder System which is working fine on a DBC3C40 development board which includes a Cyclone III FPGA.

Now I got the new version of the devlopment board DBC4CE55 which includes a Cyclone IV E FPGA.

I was recompiling my working SOPC design and made the necessary pin changes for the new FPGA.

Now I also created new projects in NIOS II IDE (version 10sp1) for the new development board DBC4CE55. However, if I want to run the project I got the error:

Downloading elf failed. Each time he wants to verify the downloaded elf-file there is an error. The whole project is using the SDRAM.

So, the project is working on the DBC3C40 board, there are no major changes to the DBC4CE55 board, same SDRAM is used, only some pin changes are performed.

Now I've added some onchip memory to the DBC4CE55 board, and configured my linker script to run from there. In this case the NIOS application is running.

Can anyone explain this?

I tried all of the information I found about this problem in forums or google. There is also an official errata sheet from Altera where this problem is noticed.

The proposed solution from Altera to connect all memories where the program runs (in this case SDRAM) should be connected to the data master of the NIOS II is also not working.

Thanks for your help.

Rgrds Ben

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    There is a memory test software example in the Nios IDE. Compile it, run it from the on chip memory and have it test the SDRAM. It should help you figure out if something is wrong.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It seems to be everything all right with SDRAM, no error occurs during this test... Any other ideas?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Not sure... it could be a problem with burst accesses that aren't detected by the memory test. Is your design properly constrained and does it meet the timing requirements?

    Does the verify fail occur at the beginning of the SDRAM or somewhere in the middle?

    Do you have any hardware that could overwrite the memory?

    Did you regenerate the SOPC system before recompiling the Quartus project? I don't know if there are any Cyclone III/IV optimisations done by SOPC builder. Probably not, but you never know...