Forum Discussion
Altera_Forum
Honored Contributor
15 years agoNot sure... it could be a problem with burst accesses that aren't detected by the memory test. Is your design properly constrained and does it meet the timing requirements?
Does the verify fail occur at the beginning of the SDRAM or somewhere in the middle? Do you have any hardware that could overwrite the memory? Did you regenerate the SOPC system before recompiling the Quartus project? I don't know if there are any Cyclone III/IV optimisations done by SOPC builder. Probably not, but you never know...