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Altera_Forum's avatar
Altera_Forum
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16 years ago

Error after switching to NIOS 9 sp2

Hi,

I was using NIOS Version 8.1 for a while. Now we are trying version 9 sp2 on the same machine. We have succesfully created new sof and ptf file.

And successfully compile the code in NIOS 9 sp2. It is also successfully opened Quartus 9 Programmer from NIOS Tools->Quartus2 Programmer.

The problem is here: When I run the HW Configuration from "Run->Run" button, it is giving me following error:

--- Quote Start ---

There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary.

--- Quote End ---

I tried the following suggestions(see last post in the link) in the forum but that didn't work.

http://www.alteraforum.com/forum/showthread.php?t=18867&highlight=version+9

Please guide me, what can I do? I am trying this for last two days but still no success.

Thanks in Advance.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    In the 'run' menu click the load JDI button, the instance ID of the debug module may have been modified during the Quartus II compilation which would cause the mismatch. If you want to see the ID open up the Nios II command shell and type 'jtagconfig -n'. I think the ID changed recently changed so if the JDI button idea doesn't work post what you see output from jtagconfig and I can probably help out. Also if you are using a Cyclone/Stratix II or earlier Nios II development board make sure you set the Quartus II unused I/O to input tri-state. This has to do with the reconfig_n pin and how it may get pulled low causing the MAX part to download an image from CFI flash immediately after your program the .sof file.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for replying.

    When I clicked on "load JDI" button, it is asking me to open the .jdi file. I don't know from where to open that because I have been given only .sof and .ptf file by our designer. In the box opposite to that button the following is written:

    --instance=1

    I tried to run the command "jtagconfig -n" and following appeared:

    1) USB-Blaster[USb-0]

    020B40DD EP2C35

    Node 11104600

    Node 0C006E00

    Please let me know, what can I do next?

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    ask him for the jdi

    or...

    for most cases use this line:

    --instance=0
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I tried to change:

    --instance=1 to --instance=0

    And press the "Run" button, it is now giving the following error.

    I will ask for jdi as well.

    --- Quote Start ---

    Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

    Pausing target processor: OK

    Reading System ID at address 0x06421558:

    ID value does not match: read 0xFFFFFFFF; expected 0x3DE92947

    Timestamp value does not match: image on board is older than expected

    Read timestamp 11:59:59 1970/01/01; expected 14:21:45 2009/11/10

    The software you are downloading may not run on the system which is currently

    configured into the device. Please download the correct SOF or recompile.

    Restarting target processor

    --- Quote End ---

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The .jdi file is generated in your hardware folder where the Quartus II project files live. Basically there can't be two identical instance ID values in an FPGA design so Quartus II sometimes has to re-assign them on the fly which would cause the ID to be different than what's programmed in the .ptf/.sopcinfo file. Loading the .jdi file is the only way to make sure the IDs are consistant across the tools.

    Judging by your console output you want to force the instance number to 0 which loading the .jdi should do for you. The top node is the Nios II JTAG debug module and the other one is the JTAG Uart. The last two digits of the node ID is the instance ID so you have instance IDs of 0 for both the debug module and JTAG uart. There is more information about this stuff in the embedded design guide that you can download from either the Nios II or SOPC Builder literature pages on www.altera.com (http://www.altera.com)

    You might have a timing violation causing the value to be read back wrong. Someone was asking me about this same issue the other day so when I run into them I'll ask them how they worked around this issue in their design.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    System IDs mismatch? uhm... look like the sof file doesn't correspond to the PTF files. Any change to the PTF file(in SOPC) must be followed by a recompilation of the FPGA image. Well another posibilites it's a timing villation, where the systemn ID cannot be readed right. I suggest a simple recompilation... and ask him for the jdi! :D

    Bye men!