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Altera_Forum
Honored Contributor
Honored ContributorDoes a NIOS II need reset?
Folks,
I recently began porting my NIOS II design to its final hardware platform from the 1C20 eval board. During this effort, I eliminated reset by assigning it internally to '0'. My logic uses active high-reset so all the reset logic and routing disappeared. The NIOS II uses active low reset so its reset is inverted before entering the NIOS II component. When reset is set '0' (inactive), the NIOS II core did not boot. I tested this by supplying reset only to the NIOS II component. When I did this, the NIOS II booted normally (all this testing done on the 1C20 eval bd). Does the NIOS II core need a reset? I thought I got one for "free" when the device configured.16 Replies
Altera_ForumNot sure what you mean by that since you figured out the NIOS core will not function without it.
Pretty much any processor needs a reset so that it starts at the correct reset location (if you power up a processor in an undefined state, you don't have a clue how it could react in some situations). Also keep in mind the symbol you are looking at on the screen in your block diagram is not just the NIOS processor in, but the whole SOPC system. Removing reset logic from the rest of those devices is not a good idea for two reasons: 1) you will not know their behaviour since they are not your core 2) designers don't put in resets for no reason at all.- Altera_Forum
But, I thought after configuration, all internals of the FPGA should be in the reset state?
I did several design s in the past with SpartanXL components from the manufacturer known as X. There it was no problem at all. I believe if it is a processor, or a state machine (whats the difference?) or something else, it shouldn't matter. Stefaan - Altera_Forum
Oh after downloading his hardware design (thought he was talking about downloading just his code using the IDE). Yes when you download your system design the reset will get triggered, however it's a good design practice to put resets in yourself. Sometimes but not often you can have a PLD not come out of reset properly.
As to your other question, a state machine is different from a processor (althought it's not impossible to make a processor from a state machine, but you'll need to lock yourself in a room for years to achieve this) in that it usually has a finite number of states. They are useful for systems that are not too complicated, but a processor has data stored as variables, so the number of states your processor can have is every combination of values over all memory locations (so lets just call that an infinite state machine). If you want to see the logic behind a state machine go to the templates in Quartus and call up the state machine with the asyn. reset and that may explain the structure to them (a condition to make you change/stay in a state, and an output dependent on the state you are in). - Altera_Forum
The Nios II was designed to operate in an FPGA or in a hardcopy/ASIC implementation.
In the latter, the RAMs internal to the Nios II (e.g. register file and caches) are not initialized on poweron. The Nios II uses the reset to guarantee that register zero actually contains zero and that the line in the icache associated with the reset address is invalidated. To properly test this logic on an FPGA, we initialize the contents of the register file and cache RAMs to non-zero values. So, the upshot of this is that you need to use the reset to get the CPU into a proper state. - Altera_Forum--- Quote Start --- originally posted by badomen@Nov 20 2004, 01:12 AM as to your other question, a state machine is different from a processor (althought it's not impossible to make a processor from a state machine, but you'll need to lock yourself in a room for years to achieve this) in that it usually has a finite number of states. they are useful for systems that are not too complicated, but a processor has data stored as variables, so the number of states your processor can have is every combination of values over all memory locations (so lets just call that an infinite state machine).
if you want to see the logic behind a state machine go to the templates in quartus and call up the state machine with the asyn. reset and that may explain the structure to them (a condition to make you change/stay in a state, and an output dependent on the state you are in). --- Quote End --- I mean a state for reading memory, do something with the data (e.g. add, load program counter, start new state machine for microcode, ...), update address (program counter), read from memory, .... My biggest problem after designeing a processor is the toolset (porting a compiler, ...). That's why I use Nios. Stefaan
- Altera_Forum
TO_BE_DONE
- Altera_Forum
If you left that out then the first couple of clocks coming out of the PLL may not be stable (that's what the delay on the reset is for in the reference designs). Your design may work, but I wouldn't trust a circuit on the first clock after being reset from configuration.
Is there a particular reason why people are interested in this? - Altera_Forum
hello BadOmen,
you said"I wouldn't trust a circuit on the first clock after being reset from configuration. " i.e. the delay designed for the reset from configuration not from the pin PLD_CLEAR_N. is it right? - Altera_Forum
About the PLL.
You can use the locked output from the pll to and (afterinversion) with the reset pin in the top level, and use this for reset to all modules. Even with no external reset this should (?) work. Stefaan - Altera_Forum
> You can use the locked output from the pll to and (afterinversion) with the
> reset pin in the top level, and use this for reset to all modules. The locked signal will toggle prior to actual phase lock -- this can cause some problems ;-) I still use a delay (along with the pll lock) to drive reset.
