Does a NIOS II need reset?

The Nios II was designed to operate in an FPGA or in a hardcopy/ASIC implementation.

In the latter, the RAMs internal to the Nios II (e.g. register file and caches) are not initialized

on poweron. The Nios II uses the reset to guarantee that register zero actually contains zero

and that the line in the icache associated with the reset address is invalidated.

To properly test this logic on an FPGA, we initialize the contents of the register file and cache

RAMs to non-zero values.

So, the upshot of this is that you need to use the reset to get the CPU into a proper state.