Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Does a NIOS II need reset?

Folks, I recently began porting my NIOS II design to its final hardware platform from the 1C20 eval board. During this effort, I eliminated reset by assigning it internally to '0'. My ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

If you left that out then the first couple of clocks coming out of the PLL may not be stable (that's what the delay on the reset is for in the reference designs). Your design may work, but I wouldn't trust a circuit on the first clock after being reset from configuration.

Is there a particular reason why people are interested in this?