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Altera_Forum's avatar
Altera_Forum
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15 years ago

DMA Problems

Hi there !!

I´ve got problems using dma controller in sopc builder, quartus 8.0 and cyclone III. I try to write about 16000 values of a 32 bit word from one memory to another.

in a first test these words a stored into an internal memory, starting dma enforces a continous transfer to an external sdram. this works fine, so values stored in external ram are correct and every clock cycle (80MHz) one word is written to the memory.

but, if i store these values in external sram and to copy this data via dma controller into the onchip mem something went wrong. for the first four clock cycles one word is written each cycle, but then outputenable goes high for 3 cycles (no data is written) followed by taking output enable low again and write another block of 4 words...it´s like a periodical behaviour. anyway, the values are transfered correctly but i want to get rid of this gap while sending data..

anyone knows how to do ???

thanks a lot..

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It looks like the DMA controller is waiting while the SDRAM read burst completes - which is probably expected.

    The write request is buffered withing the SDRAM interface - so and early acknowledge can be given to the write bus cycles.

    I'm not sure how you'll get a dma controller to overlap the SDRAM read enough.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    ok...but i´m quite confused couse it works in one direction..

    internal memory is one of the fastest memory i can implement with sopc builder i reckon..so if i write from sdram into internal memory, there should be no problem with timing..i also tried instead of writing into internal memory writing on an pio...but same result. it seems like dma controller is reading data from sdram and buffering, and while writing to master write adress isn´t able to read data from sdram at the same time...

    phhhh... :mad:
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You have misunderstood me :-)

    When anything does a write cycle, it is possible for the addressed target to just latch the address and data and immediately return 'write complete' to the initiator. This happens all over the place, and is usually called a 'posted write'. This makes it relatively easy to support zero wait-state writes.

    With reads you can't do that, the initiator needs to be told when the read completes (it wants the data!).

    For a random address the SDRAM interface has to pass the high (row) address bits to the chip, then the low (column) address bits, then it can clock through a short burst of data (probably four 32bit words).

    For sequential reads part of the previously read burst can be returned, and the 'row' address didn't be sent if it doesn't change.

    But every 4 transfers it will have to do a real SDRAM access.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    thanks for help...this is also what i expected yesterday evening. anyway copying with dma is much faster than anything else...are you also experienced with configuring a scatter gather dma controller ?

    i also found out, if configure dma in burst mode and set burst length to 1024 words, it´s possible to send 1024 in a row without a gap in between.. but length for one burst is limited to this number of words...

    thanks