DMA Problems

You have misunderstood me :-)

When anything does a write cycle, it is possible for the addressed target to just latch the address and data and immediately return 'write complete' to the initiator. This happens all over the place, and is usually called a 'posted write'. This makes it relatively easy to support zero wait-state writes.

With reads you can't do that, the initiator needs to be told when the read completes (it wants the data!).

For a random address the SDRAM interface has to pass the high (row) address bits to the chip, then the low (column) address bits, then it can clock through a short burst of data (probably four 32bit words).

For sequential reads part of the previously read burst can be returned, and the 'row' address didn't be sent if it doesn't change.

But every 4 transfers it will have to do a real SDRAM access.