Altera_Forum
Honored Contributor
13 years agoDDR3 controller UNIPHY Creating an Avalon MM master
I have a Qsys system with a DDR3 UNIPHY controller instantiated and it works. I can read and write from Nios and I can use a DMA engine to pull data and stream it over the ethernet.
But I am having trouble creating a master to drive the DDR3 controller. I want to be able to buffer up data in the DDR3 using my own logic block with a MM master port. I have the block created and have it connected in my QSYS system but am never able to get the waitrequest signal to show up in my block from the DDR3 controller. I have a signal tap and can see the "avl_ready" signal coming from the ddr3 controller but it does not appear to be connected to my blocks' wait request signal. Does anyone have an example MM master that drives a DDR3 controller?