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Honored Contributor
Honored ContributorDDR3 controller UNIPHY Creating an Avalon MM master
I have a Qsys system with a DDR3 UNIPHY controller instantiated and it works. I can read and write from Nios and I can use a DMA engine to pull data and stream it over the ethernet. But I am ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Address is 32bit wide,but addr[31] is a cache flag.so there is just 2G byte in avalon bus that you can access. when addr[31] is 1,it means no cache access. --- Quote End --- I do know about the cache bypass. My memory only uses 29 bits (0x1FFFFFFF) of byte addressable memory space. I'm not asserting bit 31 or trying to use it. that would be 0x8XXXXXX
