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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR3 controller UNIPHY Creating an Avalon MM master

I have a Qsys system with a DDR3 UNIPHY controller instantiated and it works. I can read and write from Nios and I can use a DMA engine to pull data and stream it over the ethernet. But I am ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I got it working by moving my DDR3 controller to base address 0x00000000 in the system. The avalon writedata port on the DDR3 controller is 128bits wide so when I increment my address on the custom master, I increment by 0x10 (16 bytes or 128bits) at a time and everything is working nicely. This gets translated by the fabric and I can see the lower 4 bits of my master write address port are removed and the DDR3 controller is writing in 128bit chunks.

The question is how to get a non zero base address to work? If my DDR3 controller is at base address 0x10000000 and spans 0x1FFFFFFF; What address should I put out on my custom masters' write address port? I was trying to use 0x1XXXXXXX without luck. What am I doing wrong? I assumed everything that you did over the avalon interface was byte addressable, is this not the case?