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Honored Contributorcreating sram component problems
hi,i'm creating my own sram with the component editor.i've assigned signals as address,data,chipselect,write/read enable,output enable,with the interface avalon_slave_0,is there anything else that i have to assign ?and do i have to write VHDL files?
5 Replies
Altera_ForumThere is no need for VHDL files in a simple SRAM interface. You need to set the signal direction, I do not know exactly which signals should be inputs and which outputs, but SOPC builder will probably warn you. You need a clock signal which will not be visible on the created bus but is used for timing. You have to set the timing for the component.
IzI- Altera_Forum
thank you very much for your answer.it seems that the sram does not need a clk signal, the write/read enable signal is used as replacement.but the SOPC Builder warns that a clk signal is needed because the sram is defined as avlon-slave component.so do i have to define the write/reda signal as the clk signal?
- Altera_Forum--- Quote Start --- originally posted by cicizhang@Nov 17 2006, 04:59 AM thank you very much for your answer.it seems that the sram does not need a clk signal, the write/read enable signal is used as replacement.but the sopc builder warns that a clk signal is needed because the sram is defined as avlon-slave component.so do i have to define the write/reda signal as the clk signal?
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--- Quote End --- The SRAM interface is of type "tristate slave", not "avalon slave". Take a look towards the end of the "Building memory sub-systems" chapter in the SOPC Builder sub-section of the Quartus II handbook. You should see everything you need there. - slacker
- Altera_Forum
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif thank you so much!
- Altera_Forum
it helps a lot.
