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originally posted by cicizhang@Nov 17 2006, 04:59 AM
thank you very much for your answer.it seems that the sram does not need a clk signal, the write/read enable signal is used as replacement.but the sopc builder warns that a clk signal is needed because the sram is defined as avlon-slave component.so do i have to define the write/reda signal as the clk signal?
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The SRAM interface is of type "tristate slave", not "avalon slave". Take a look towards the end of the "Building memory sub-systems" chapter in the SOPC Builder sub-section of the Quartus II handbook. You should see everything you need there.
- slacker
Honored Contributor
