Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

creating sram component problems

hi,i'm creating my own sram with the component editor.i've assigned signals as address,data,chipselect,write/read enable,output enable,with the interface avalon_slave_0,is there anything else...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

There is no need for VHDL files in a simple SRAM interface. You need to set the signal direction, I do not know exactly which signals should be inputs and which outputs, but SOPC builder will probably warn you. You need a clock signal which will not be visible on the created bus but is used for timing. You have to set the timing for the component.

IzI