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Altera_Forum's avatar
Altera_Forum
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20 years ago

Create a new componet(Avalon tristate)

1)

As the components are share the system data/ address bus in the custom board, so we should "share" the bus. Then we found there is no "place" to set "is share " opition, only in the "tristate slave" interface , it will automatic share data/address when we check the class.ptf. And when you use "Tristate slave ", you don't need "export" any signal, as the signals of "tristate slave" will be automaticly "exported", too. Is it right?

2)

As we know the tristate slave is byte address, something like the dynamic alignment, so we keep it in our mind when we add such kind slave, always setting them "memory" in the "interface Tab". But we find Lan91c111 using "Native" and "IORD_16DIRECT". We think it is fine,too. But it will waste lot's of address space, as "Native" alignment is DWORD alignment. Why? Is it a guideline?

3)

We find the "BIG" differences between the "class.ptf" in the <componets> path , providing by ALTERA and the "class.ptf" created by the "New component", then we search "ptf reference" datasheet, but ALTERA web says it move to "quautus handbook" , but we still cannot find it in the latest handbook. Where?

4)

At last, we&#39;d like to suggest ALTERA to give more examples about:

a) How to create kinds of components , include share or not share ones,maybe give us comments of how to create the providing components.

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif how to set all the opitions, such as hold time, set time, is share.... in the GUI or how to manully modify the "class.ptf".

Is it necessary to Let us to manage the "another" language "class.ptf"? Think it , how many "language" we should learn before we are comfortable in "NIOS" world, HDL, C, Perl.....

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    I use "New componet" to create LCD module(quartus 4.2 Nios II 1.1)

    (1)

    LCD module: RDn, WRn, CSn, Data[7..0], A0

    In the custom board, A0 is connected to Avalon&#39;s tristate address[0], which is shared by SRAM.

    (2)

    SOPC components: LCD

    Interface: Avalon tristate slave

    Addressing: Memory

    signal name_______type__________direction

    RDn_____________readdata_n_____in

    WRn____________writedata_n_____in

    CSn_____________chipselect_n____in

    Data[7..0]________data__________inout

    A0______________address_______in

    It will share Data[7..0] and A0 in tristate bus automaticly.

    (3)

    The result is not work now. Some questions:

    (3.1) is it the problem of using IORD/IOWR in such way:

    IORD_8DIRECT(LCD_base,0)

    IOWR_8DIRECT(LCD_base,0,data8)

    IORD_8DIRECT(LCD_base,1)

    IOWR_8DIRECT(LCD_base,1,data8)

    causing multi-times read/write cycle or the address not diving by 4?

    (3.2) If I change it to register addressing, is it conflect by "A0 is connected to Avalon&#39;s tristate address[0]" ( should connected to Addrss[2])
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Do you use an 8, 16 or 32-bit data bus off-chip?

    In any case, I would suggest you use Native (Registered) mode, and connect the SOPC A2 signal to the A0/RS0 on the LCD controller device. "Wasting" a few addresses like this is completely irrelevant.

    Your code would then do:

    IORD_8DIRECT(LCD_base,0)

    IOWR_8DIRECT(LCD_base,0,data8)

    IORD_8DIRECT(LCD_base,4)

    IOWR_8DIRECT(LCD_base,4,data8)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi, JasonDiplomat

    There are:

    8-bit LCD

    16-bit Ethernet

    32-bit SRAM

    sharing the Avalon tristate bus.