Create a new componet(Avalon tristate)

I use "New componet" to create LCD module(quartus 4.2 Nios II 1.1)

(1)

LCD module: RDn, WRn, CSn, Data[7..0], A0

In the custom board, A0 is connected to Avalon's tristate address[0], which is shared by SRAM.

(2)

SOPC components: LCD

Interface: Avalon tristate slave

Addressing: Memory

signal name_______type__________direction

RDn_____________readdata_n_____in

WRn____________writedata_n_____in

CSn_____________chipselect_n____in

Data[7..0]________data__________inout

A0______________address_______in

It will share Data[7..0] and A0 in tristate bus automaticly.

(3)

The result is not work now. Some questions:

(3.1) is it the problem of using IORD/IOWR in such way:

IORD_8DIRECT(LCD_base,0)

IOWR_8DIRECT(LCD_base,0,data8)

IORD_8DIRECT(LCD_base,1)

IOWR_8DIRECT(LCD_base,1,data8)

causing multi-times read/write cycle or the address not diving by 4?

(3.2) If I change it to register addressing, is it conflect by "A0 is connected to Avalon's tristate address[0]" ( should connected to Addrss[2])