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drbarryh's avatar
drbarryh
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6 days ago

Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA

Greetings all ALTERA Experts,

Can somebody please provide some guidance (e.g. links to example designs and App notes etc.) showing how to implement an mSGDMA based system using a NIOSV/m processor on a MAX10 FPGA?

The first problem is where to find the best and most up to date Documentation and any example designs actually using the mSGDMA. With clear descriptions of how the data and control flow works, hopefully describing how descriptors are created and then used by the mSGDMA IP cores.

Another area of concern is how to wire up mSGDMA IP cores correctly in a Qsys platform (to both data and descriptor memory etc.), and with both the prefetcher and burst mode enabled. I want to use one mSGDMA with an AVALON MM -> AVALON ST flow and a second for AVALON ST -> AVALON MM Flow. 

Then the next area of concern is how to write a HAL based driver with the NIOSV/m processor to interact with mSGDMA IOP cores.

Thanks for any help,

Dr Barry H

 

general
Nios Architecture
Nios Cpu

12 Replies

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 day ago

    Hello Dr. Barry,

    I think the file was not uploaded successfully. this might be due to the file size limit. I sent you a DM, kindly check it.

     

    Thank you,

    Fawaz.

  • SueC_Altera's avatar
    SueC_Altera
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    6 days ago

    Hi Dr. Barry H,

    I put the link in my text, but it didn't work! :-(

    It also won't let me just paste the link.  I don't know why!  Paste this link in your brower: 

    https://www.intel.com/content/www/us/en/design-example/843487/agilex-7-nios-v-m-processor-with-ddr-dma-and-ocm-design-example.html

    Sue

    • tehjingy_Altera's avatar
      tehjingy_Altera
      Icon for Regular Contributor rankRegular Contributor
      2 days ago

      Hi drbarryh 

       

      The link shared by SueC_Altera is the one you are looking for.

      It is using the NiosV processor core with the mSGDMA IP. 

      It is for the Agilex7 but you could recreate the hardware connections in the project for the device that you want.

       

      Do take note on the naming of the par. It should be top.par and not top(x).par if you have downloaded multiple.

      But once you managed to unzip the par, you should go thorugh the IP Upgrade which is prompt when you open the project for the first time.

       

      In the project folder you could see a folder names "sw" in it you could see a main source that you could reference on accesssing the mSGDMA IP from the NiosV processor.

       

      • drbarryh's avatar
        drbarryh
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        2 days ago

        HI tehjingy,

        Thanks for confirmation. However when i try to open that top.par file in any version of quartus from 24.1 to 25.1 all it ever says it that the template load failed. Can you say which exact version of Quartus to use and what the procedure should be to get that par file to extract into a quartus project please ?

        Thanks for your help, Dr Barry H

    • drbarryh's avatar
      drbarryh
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      3 days ago

      Hi Sue, unfortunately i installed Quartus Prime Pr version 25.3.1 (the latest) and that failed to unravel the PAR file. I will install the version cited to work which was 24.3.1 and try again ! Also the board used is now showing as obsolete as well.

      Any idea if there is another ALTERA example design using a NIOSV processor and the mSGDMA IP core i could use ?
      Thanks, Dr Barry H

      • FawazJ_Altera's avatar
        FawazJ_Altera
        Icon for Frequent Contributor rankFrequent Contributor
        1 day ago

        Hello Dr. Barry,

        It’s recommended to use the same Quartus Prime version that was originally used for the design. This helps avoid project migration issues that could alter IP behavior and potentially introduce untested or unexpected results.

        I was able to extract the file and have compressed it, it’s attached here. Please let me know if you’re able to download it successfully.



        Thank you,

        Fawaz

    • drbarryh's avatar
      drbarryh
      Icon for Contributor rankContributor
      6 days ago

      Thanks Sue, yes this text boxing can be picky can't it ! Right the link you sent me worked and i can see an AGILEX 7 example design PAR file and it does at least have DMA in it so that is a better start !

      Thanks for the help, Dr Barry H

  • SueC_Altera's avatar
    SueC_Altera
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    6 days ago

    Hi Dr. Barry H,

    I'm sorry - I thought the DMA was in the Agilex 5 design.  We do have an Agilex 7 design you could adapt to Max 10

    Sue

    • drbarryh's avatar
      drbarryh
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      6 days ago

      Hi Sue,

      No problem.....ALTERA does have a huge database full of just about everything, and i know it is hard to apply the right filters so that you get the right things sometimes (always!).

      Yes please if you can point me to that AGILEX 7 + mSGDMA example design and if i can unzip it and see it in a Platform on Quartus it would help to get me started i hope.

      Cheers, Dr Barry H

  • SueC_Altera's avatar
    SueC_Altera
    Icon for Contributor rankContributor
    6 days ago

    Hi Dr Barry H,

    I don't see that exact example.  There's a Nios V on Max 10 example here. There's a Nios V with mSGDMA on Agilex 5 here. I wonder if you can use those to figure out what you need to know.  Please let me know.

    Thanks,

    Sue

    • drbarryh's avatar
      drbarryh
      Icon for Contributor rankContributor
      6 days ago

      Hi Sue,

      Thanks for the 2 links .....but neither seem to be very useful to me to be honest. The first one doesn't show anything about an mSGDMA or any other DMA and i can't see any mention of using an mSGDMA on the Agilex 5 example either, plus i don't have an Agilex 5 Premium board or Quartus Prime Pro (i am working with Quartus Standard edition 25.1 and a MAX10 Development board). Thanks for trying though. I will continue my quest !

      Best regards,

      Dr Barry H