CIII/EPCS design configures and programs but does not start

Hi Mark

I do nearly the same with a CIII and it works.

Compare my steps to yours, although the differences are (apparently) irrelevant.

1- sof2flash --epcs --input=logic.sof --output=logic.flash

2- elf2flash --epcs --after=logic.flash --input=firmware".elf --output=firmware.flash

3- nios2-configure-sof --cable='USB-Blaster [USB-1]' logic.sof

4- nios2-flash-programmer --cable='USB-Blaster [USB-1]' --epcs --base=0xa00000 logic.flash

5- nios2-flash-programmer --cable='USB-Blaster [USB-1]' --epcs --base=0xa00000 firmware.flash

Hi,

Thanks for the reply. Our steps are basically the same and I get the same with yours. Same also with the flash programmer GUI in the IDE.

I double checked that the FPGA is configuring properly from the EPCS device and it does (clocks and test points all come up as expected).

I also read back the contents of the ROM in the EPCS SOPC component to verify that it's the same as the ciii boot loader in nios2eds/components/altera_nios2/boot_loader_epcs_sii_siii_ciii.srec. It matches byte for byte. It's like the call at the end of the boot loader isn't calling the correct address.

Can you tell me what your reset and exception addresses are in your NIOS CPU? My reset address points to the EPCS so that it starts at the boot loader, which seems the correct thing to do.

Mark.

OK, but I'm using 10.1 SP1. Is the bug still in this?

When you say to use the stand-alone programmer I assume you mean the Quartus SAP. But isn't this the same code as the 10.1 SP1 release?

Thanks,

Mark.

Yes, it looks like it. I have experienced the nios2-flash-programmer. Using it to program EPCS, NIOS II does not boot properly. I have a DE2 board. It is proven to me that nios2-flash-programmer has a bug.

One more thing, stay with uncompressed programming file. The compress one may have problem too. I have not fully investigated the issue yet.

So, bottom line. I use SAF to program EPCS with uncompressed pof.

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Can you tell me what your reset and exception addresses are in your NIOS CPU? My reset address points to the EPCS so that it starts at the boot loader, which seems the correct thing to do.

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Hi Mark

My Reset address is the EPCS base address, while exception address is the base address of onchip code memory + 0x20.

I use 9.0 sp2 and I was not aware of the reported bug. I used nios2-flash-programmer but I never had problems. I use compressed bitstreams, too.

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So, bottom line. I use SAF to program EPCS with uncompressed pof.

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OK, tried that. It doesn't work either. I create a HEX file of the software offset to the end of the FPGA data. I create a POF file starting with the FPGA data and followed by the HEX file. The software complains that they overlap by one byte (they don't). So I shift the HEX data by one byte to make the SAP happy and generate the POF. It generates the POF, which successfully programs the FPGA but doesn't start the software in the same way as before.

Mark.

Hi Mark.

I think you definitely have a problem with the Nios 2 bootloader.

Since you initially said you made the same with other devices (and it worked fine!!), it could be that your are using the bootloader of the wrong device, because you did a copy and paste with old project files. Or maybe bootloader image has been corrupted because of any other reason.

The bootloader is usually stored in a epcs_controller_boot_rom.hex file in the fpga project.

It is generated from the bootloader source files in Altera directory

C:\altera\<your version>\nios2eds\components\altera_nios2\boot _loader_sources\boot_loader_epcs_bits_<device_fami ly>.S

I'd recommend you check the hex file and possibly regenerate it from the source files.

I attach for your convenience my CIII bootloader file. It should work for you, too.

Execute a fpga MIF update, flash into epcs and let me know if this solves your problem.

Regards

Cris