cal_uart(with fifo) + NIOSserial.c

It will be very difficult to debug on the same serial console. You'd better use jtag as console, to test the new uart on some other port.

You can use printk() then.

I use the cal_UART instead of the UART,then generate cpu_name.ptf, compared with the old cpu_name.ptf, there is no the list information in the new cpu_name.ptf!

who can help me ?

1.

PORT_WIRING

{

PORT rxd

{

direction = "input";

width = "1";

Is_Enabled = "1";

}

PORT txd

{

direction = "output";

width = "1";

Is_Enabled = "1";

}

PORT cts_n

{

direction = "input";

width = "1";

Is_Enabled = "0";

}

PORT rts_n

{

direction = "output";

width = "1";

Is_Enabled = "0";

}

}

I can get

PORT rxd
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT txd
{
direction = "output";
width = "1";
Is_Enabled = "1";
}

and rts_n, cts_n are depent to your setup during add cal_uart to NiosII in SOPCbuilder.

We tested the cal_uart's irq signal is only active for 1 clock period so

I changed

<cal_uart>/uart_pm.pl:L1933:rx_char_ready to rx_not_empty

in order to

irq <= ... rx_not_empty ...

then it worked well.

Can anyone tell me how to obtain the CAL_UART design please?

* Edited* Got it now. many thanks

Hi all,

I am trying the cal_avalon_uart core, but I get some problems.

I tried to do as mountain8848 said :

change rx_char_ready to rx_not_empty at line 1933

But I still get communication problems with uClinux. I only receive chars after 64 bytes are in the FIFO (the FIFO is 64 bytes long). SO an interrupt is only generated when the fifo is completely full. The main problem is that after it worked once or twice (64 or 128 bytes received), uClinux crashes (no response on any console).

Did someone fix this ?

Thanks for help

Regards

Pierre-Olivier

We were able to get the cal_uart working fully only after modifying the verilog code.

It seems that it only supports polling mode cleanly.

When using interrupts, it doesn&#39;t generate them in a way that takes advantage of the fifo&#39;s.

We had to modify our verilog code so that interrupts were generated only when the fifo was 75% full for example.

This was done by changing the "qualified_irq" assignment.

Until we made the modifications, the cal_uart component didn&#39;t perform any different than the normal Altera_Avalon_Uart.

in n2cpu_nii5v1.pdf p45, It is said " By peripheral design, an IRQ bit is guaranteed to remain asserted until the processor explicitly responds to the peripheral."

If we did not changed anything with FIFO_UART(cal_uart), the irq is a pulse, which duty cycle is one period of the system clock.

So we change rx_char_ready to rx_not_empty at line 1933 so it will generate the IRQ properly----generate irp until NiosII deassert it by read all datas from FIFO.And we tested FIFO_UART with original NIOSserial.c

In our opinion:

1. FIFO_UART does generate IRQ as soon as it received one byte

2. During uClinux IRQ server, FIFO_UART dose receive any bytes to FIFO if there are datas in the RXD line ---- this is one of benefits of FIFO.

3. NIOSserial.c does receive all datas from FIFO_UART untill FIFO is empty and IRQ will deassert.

Then things happen again and again.

Like trk_golf said, It will be grate if the IRQ generates at 75% full of FIFO. But it should be add a Timer to tell the us there are datas in FIFO, which maybe never get 75% full of FIFO. We did not work out this method. Any helps about this will be appreciate!

PS: After change the SOPC components perl scripts file , you should regenerate NiosII in SOPC builder, recompile in Quartus, re-debug in uClinux.

Thanks for the replies,

So it acts like I expected, but I don&#39;t understand why uClinux crashes then.

When I cat the serial port (cat /dev/ttyS3), it works for around 128 chars, then linux crashes.

Is there any explanation to this ?

Thanks

Pierre-Oliver