cal_uart(with fifo) + NIOSserial.c

in n2cpu_nii5v1.pdf p45, It is said " By peripheral design, an IRQ bit is guaranteed to remain asserted until the processor explicitly responds to the peripheral."

If we did not changed anything with FIFO_UART(cal_uart), the irq is a pulse, which duty cycle is one period of the system clock.

So we change rx_char_ready to rx_not_empty at line 1933 so it will generate the IRQ properly----generate irp until NiosII deassert it by read all datas from FIFO.And we tested FIFO_UART with original NIOSserial.c

In our opinion:

1. FIFO_UART does generate IRQ as soon as it received one byte

2. During uClinux IRQ server, FIFO_UART dose receive any bytes to FIFO if there are datas in the RXD line ---- this is one of benefits of FIFO.

3. NIOSserial.c does receive all datas from FIFO_UART untill FIFO is empty and IRQ will deassert.

Then things happen again and again.

Like trk_golf said, It will be grate if the IRQ generates at 75% full of FIFO. But it should be add a Timer to tell the us there are datas in FIFO, which maybe never get 75% full of FIFO. We did not work out this method. Any helps about this will be appreciate!

PS: After change the SOPC components perl scripts file , you should regenerate NiosII in SOPC builder, recompile in Quartus, re-debug in uClinux.