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Altera_Forum
Honored Contributor
19 years agoWe were able to get the cal_uart working fully only after modifying the verilog code.
It seems that it only supports polling mode cleanly. When using interrupts, it doesn't generate them in a way that takes advantage of the fifo's. We had to modify our verilog code so that interrupts were generated only when the fifo was 75% full for example. This was done by changing the "qualified_irq" assignment. Until we made the modifications, the cal_uart component didn't perform any different than the normal Altera_Avalon_Uart.