Booting From Flash

Firmware booting means telling the nios cpu its reset address at which to load and execute the first instruction....

These boot instructions can be anything. an external flash device, and internal memory or even hard coded as logical combinatorial euqation depending on nios adress.

cfi means this flash device is compatibel to other device so you do not need to write your own programming software and can use the cfi information table from this device to automatical run specific routines. like intel programming algorithmn.

it is also possible to create some kind of custom ip functionality that opens a memory window to nios and forms the nios adress into a serial stream like spi to read an write from an external device, holding nios with waitstates until external execution is finished.

i has implemented a custom ip block that controls nios reset execution adress, by using an external signal to load different op codes.

assign readata = ( externalsignal ) ? 12345678 : 876543210;

this veriloag assignment is in deep larger and nios executed different op code depending on externalsignal and at the end jumps to different memory location as alternate boot address.

<div class='quotetop'>QUOTE (MSchmitt @ Jul 30 2009, 03:56 PM) <{post_snapback}> (index.php?act=findpost&pid=23343)</div>

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Firmware booting means telling the nios cpu its reset address at which to load and execute the first instruction....

These boot instructions can be anything. an external flash device, and internal memory or even hard coded as logical combinatorial euqation depending on nios adress.

cfi means this flash device is compatibel to other device so you do not need to write your own programming software and can use the cfi information table from this device to automatical run specific routines. like intel programming algorithmn.

it is also possible to create some kind of custom ip functionality that opens a memory window to nios and forms the nios adress into a serial stream like spi to read an write from an external device, holding nios with waitstates until external execution is finished.

i has implemented a custom ip block that controls nios reset execution adress, by using an external signal to load different op codes.

assign readata = ( externalsignal ) ? 12345678 : 876543210;

this veriloag assignment is in deep larger and nios executed different op code depending on externalsignal and at the end jumps to different memory location as alternate boot address.[/b]

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Dear MSchmitt,

Thank you for your response. Are you able to clarify some things though. Up until now we have used the EPCS to store frimware and we have set the reset set address of the NIOS CPU to the EPCS controller and on reset the firmware has loaded successfully, automatically with no additional development required. We also used this method for a double CPU project where the same firmware was required for both CPU&#39;s. For this design we needed to incoprate additional logic to control the resets to the CPUs to ensure that the firmware was booted from the EPCS successfuly. Now we need to design a multi-processor (3+) design with different firmwares for each CPU. We don&#39;t want to rely on the previous design using the EPCS because our experience lead us to believe that the EPCS was really only meant to be used for a storing and booting a single CPU and not a multiple processor system (well that is what Altera told us a number of years ago ! ). Now when I was looking through the Altera literature they mention booting firmware for a multi-porcessor design from an external flash device (or multiple external Flash devices). They state that the reset address for the specific cpu must be set to the right address range within that external flash device. Thus the boot loader knows where to turn on reset to copy to the firmware from. However how does the boot loader access the external flash? The FLash Programmer User Guide states that the Altera FLash programmer can program an external flash that is CFI compliant. I assume that if I use such a device (one that is CFI compliant) then I simply add a common flash interface within the SOPC system and set my reset address to the correct address range within the CFI/external flash and on reset the boot loader will do the rest. But what hapenns if I want to use an external flash device that is not CFI compliant (e.g. a serial flash /SPI) ? How do I program it (it sounds like I will not be able to use the ALtera Flash Programmer ?) and how do I boot from it ? Do I have to create a customize component to do this work ? If yes, how and what - is there any documentation on this ?

How do most people work with multi-processor designs ? What type of external flash devices do they use and how do they program them and boot from them ?

An EPCS device is just an OEMed serial (SPI) flash...nothing more. I think you&#39;d just have to come up with a flash override file describing how large the flash is and each of its sectors.

Cheers,

- slacker

<div class='quotetop'>QUOTE (slacker @ Aug 2 2009, 09:01 PM) <{post_snapback}> (index.php?act=findpost&pid=23373)</div>

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An EPCS device is just an OEMed serial (SPI) flash...nothing more. I think you&#39;d just have to come up with a flash override file describing how large the flash is and each of its sectors.

Cheers,

- slacker[/b]

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Dear Slacker,

Thanks for your resposne. What is a "flash overide" file and where is it implemented ? Also what do I do if I want to use a non CFI compliant flash device to store and boot my multi-processor firmware ? How would I store the firmware there and how do I boot from it ( For booting : I know that I will need to set the reset address of each processor to the area of the external flash - but how does the boot loader access the external flash ? Do I need a custom component ? How much additional development will be requried for a non compliant CFI device ?)

Also do you know what the common type of external (flash) device people use for multi-processor designs ? We need a device that we will have the fastest access to since part of our frimware will not fit within the onboard memory of our Altera chip !

Thank you in advanced

Shmuel

Hi Shmuel,

A flash override file is pretty clearly defined in the Nios II Flash Programmer User Guide. In truth, I&#39;m not 100% sure that it works with EPCS (SPI) flash devices, but it&#39;s worth a try.

<div class='quotetop'>QUOTE </div>

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How would I store the firmware there and how do I boot from it ( For booting : I know that I will need to set the reset address of each processor to the area of the external flash - but how does the boot loader access the external flash?[/b]

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Well, that depends on what type of flash it is...right? For an EPCS (SPI) flash, the bootloader is stored in a small onchip memory that is part of the epcs_controller component. For the CFI compliant flashes, the bootloader is prepended to the "payload" that you intend to attach.

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Do I need a custom component ? How much additional development will be requried for a non compliant CFI device?[/b]

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It all depends on the type of flash that you decide to use.

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Also do you know what the common type of external (flash) device people use for multi-processor designs? We need a device that we will have the fastest access to since part of our frimware will not fit within the onboard memory of our Altera chip![/b]

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CFI is probably most popular, though I don&#39;t know of many that actually run their code from it.

For your multi-CPU questions, you should browse to AN458 on the following page: http://www.altera.com/literature/lit-an.jsp (http://www.altera.com/literature/lit-an.jsp)

Cheers,

- Brendan

<div class='quotetop'>QUOTE (slacker @ Aug 4 2009, 12:39 AM) <{post_snapback}> (index.php?act=findpost&pid=23391)</div>

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Hi Shmuel,

A flash override file is pretty clearly defined in the Nios II Flash Programmer User Guide. In truth, I&#39;m not 100% sure that it works with EPCS (SPI) flash devices, but it&#39;s worth a try.

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How would I store the firmware there and how do I boot from it ( For booting : I know that I will need to set the reset address of each processor to the area of the external flash - but how does the boot loader access the external flash?[/b]

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Well, that depends on what type of flash it is...right? For an EPCS (SPI) flash, the bootloader is stored in a small onchip memory that is part of the epcs_controller component. For the CFI compliant flashes, the bootloader is prepended to the "payload" that you intend to attach.

<div class='quotetop'>QUOTE </div>

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Do I need a custom component ? How much additional development will be requried for a non compliant CFI device?[/b]

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It all depends on the type of flash that you decide to use.

<div class='quotetop'>QUOTE </div>

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Also do you know what the common type of external (flash) device people use for multi-processor designs? We need a device that we will have the fastest access to since part of our frimware will not fit within the onboard memory of our Altera chip![/b]

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CFI is probably most popular, though I don&#39;t know of many that actually run their code from it.

For your multi-CPU questions, you should browse to AN458 on the following page: http://www.altera.com/literature/lit-an.jsp (http://www.altera.com/literature/lit-an.jsp)

Cheers,

- Brendan

[/b]

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Dear Brendan,

Thank you for your quick response. If you don&#39;t mind I haeva couple of more questions

1. For non-cfi flash devices:-

a) How would I program the flash device ?

B) To boot, will I need to develop a custom boot loader ?

c) Can I use the standard Altera common flash interface controller core to acces this device or will I need to develop a custom peripheral interface ?

2. For my Multi-processor design we wish to use a single FLash device to store the firmware and other data. Will we need a MUTEX core to arbitrate the booting process and access there after to the External Flash ?

Dear Brendan,

Another question : I am looking at a Spansion CFI flash

http://spansion.com/products/support/datas...-p_00_a11_e.pdf (http://spansion.com/products/support/datasheets/s29gl-p_00_a11_e.pdf)

1. It allows for both regular read operations and page read operations (page read operations are much faster !). Using the CFI controller and IDE HAL is there some way to switch to page read operations to speed up the read access to this flash ?

2. For booting from this flash - can the standard CFI boot loader be used (and thus all I have to do is connect up the flash signals and set the correct reset address and then carry out a reset and the boot process will be automatic (assuming that I have set the correct execution adress from which the code is to be run !))?

if you use a CFI flash than there is no special controler or boot loader.

CFI is a normal parallel flash device like any other external memory like sram or any other external device like a latch or a uart or what so ever.

CFI means that this device has in addition to a non cfi flash device some information about this device (the cfi table) that gets accessible when you perfrom some certain accesses to this device. also the programming algorithm is standard. there are intel and amd algorithm. if you have an cfi conform device, you "just" need to read out the cfi table, then you know what type it is, how the sectors and other structures are setup and you can pass these information to your programming alogorithm. the benefit from this is that you can replace the device with for example a bigger one and you do not need to modify your application.

cfi also means that you can buy cfi flash devices from different manufacture and use them and do not need to worry about programming (except external hardware related stuff)

what does this mean to your questions ?

there is no ip funtionality for cfi flash.

place an avalon tristate bridge, connect externaly cfi flash and sram and what ever to that interface and thats it.

no for sopc builder you just need to specify that reset is your cfi flash device and the offset where the software starts wioth its first instruction

for multiple nios designs, lets assume cpu0 reset ist cfi_Device offsett 0x0 then cpu1 has offfset 0x10000 and cpu2 has offset 0x20000 all within the same cfi device.

now you just need to tell nios flash programmer to store application_cpu0 to 0x0 the application for cpu1 to 0x10000 and so on.

we have designs with one big flash where a maxII loads the fpga from and this flash has several application inside and an addition external ARM also boots form this device.

so there is no cfi boot loader, just tell you cpu under which adr to fetch the first instruction.

the flash override is usefull when you use a device NOT from altera. Altera and its FAE recommends to use EPCS devices but there are plenty of other devices out there from spansion for example that also do the job. you just need to create a flash overide test file (there was a thread started from me, but has not been recovered by the big loss so the collection of proved devices posted there is gone)

as slacker said, epcs is just an oem or different labled chip. spansion has a device that i would bet is the epcs64 as all information you get for the epcs64 you will find in spansion data sheet. the epcs DS has only a subset of the spansion commands.

this file holds the information about you spi device id, its internal structures and then nios flash programmer reads out your device id and looks into that file and used the information from there.

you need only this tweak with the overide to store the information with a blaster for example. nios and your application will not detect that it is not an epcs device.

as you cfi is an external device under avalon control, you will not need to controll the access of different masters. nios or dma or custom ip

the only thing you must take care about is when you write to the cfi that nobody else talks to the cfi and interupts the access.

regards

Michael

EDIT : just looked at the spansion pdf link posted here. you can use this device, i use the S29GLxx Family with BGA in serveral designs. there is no need to worry about. just solder it and use it no modification, hacks, tweaks needed. this device is fully nios compatible :-)

Dear Michael,

Thankyou so much for your very informative and detailed response. I still am a bit unlcear about something. We plan on using this external flash memory to store quite a few things. We will be running a number of processors (3+) simultaneously that may need to access this external flash for booting of firnmware and also retrieving and writing data. Also we may require data transferred from an external source to the flash device at the same time ! Won&#39;t we need some sort of arbitration device - like a MUTEX ? It could be that we might need to reset the CPU&#39;s at differnet times that may require rebooting of their firmware - will the MUTEX core handle this type of arbitration or are we going to have to incorporate an external handshake logic on the resets to the CPUs ? We did this for a previous design where we were booting a multi-core design from an EPCS. We needed to load indentical code to both processors. We had to design some complex external logic to control the system of resets so that the reset and download of one firmware would not clobber the 2nd CPUs download of firmware !?

Thanks

Shmuel

If your cfi flash is connected via an avalon tri state bridge then this bridge arbitrates the access of different masters. Meaning you can let different masters access this flash as it is a slave to avalon at the same time. Only one of them will gain access, the others must wait.

So all nios masters could start to run from this flash at the same time

Also you could add other masters like dma or your custum ip to gain access to a slave. All arbitration is handled via avalon and you setup special behavioral via sopc builder, see altera documentation

But you must take care about the following.

If one master alternates the cfi you must enshure that no other master accesses this cfi as this would disturb the programming algorithm, so have a look at the datesheet of your cfi

In your application with external cfi flash as boot medium all nios reset pointers can point to the same slave, even to the same reset adress and start at the same time. In fact the avalon bridge will multilex the access. This is very well documented by altera avalon specification.

You must take about caches, but you are aware of that already.

It would also be possible to share slaves like sdram between the different nios.