Honored Contributor
Honored Contributor<div class='quotetop'>QUOTE (MSchmitt @ Jul 30 2009, 03:56 PM) <{post_snapback}> (index.php?act=findpost&pid=23343)</div>
--- Quote Start --- Firmware booting means telling the nios cpu its reset address at which to load and execute the first instruction.... These boot instructions can be anything. an external flash device, and internal memory or even hard coded as logical combinatorial euqation depending on nios adress. cfi means this flash device is compatibel to other device so you do not need to write your own programming software and can use the cfi information table from this device to automatical run specific routines. like intel programming algorithmn. it is also possible to create some kind of custom ip functionality that opens a memory window to nios and forms the nios adress into a serial stream like spi to read an write from an external device, holding nios with waitstates until external execution is finished. i has implemented a custom ip block that controls nios reset execution adress, by using an external signal to load different op codes. assign readata = ( externalsignal ) ? 12345678 : 876543210; this veriloag assignment is in deep larger and nios executed different op code depending on externalsignal and at the end jumps to different memory location as alternate boot address.[/b] --- Quote End --- Dear MSchmitt, Thank you for your response. Are you able to clarify some things though. Up until now we have used the EPCS to store frimware and we have set the reset set address of the NIOS CPU to the EPCS controller and on reset the firmware has loaded successfully, automatically with no additional development required. We also used this method for a double CPU project where the same firmware was required for both CPU's. For this design we needed to incoprate additional logic to control the resets to the CPUs to ensure that the firmware was booted from the EPCS successfuly. Now we need to design a multi-processor (3+) design with different firmwares for each CPU. We don't want to rely on the previous design using the EPCS because our experience lead us to believe that the EPCS was really only meant to be used for a storing and booting a single CPU and not a multiple processor system (well that is what Altera told us a number of years ago ! ). Now when I was looking through the Altera literature they mention booting firmware for a multi-porcessor design from an external flash device (or multiple external Flash devices). They state that the reset address for the specific cpu must be set to the right address range within that external flash device. Thus the boot loader knows where to turn on reset to copy to the firmware from. However how does the boot loader access the external flash? The FLash Programmer User Guide states that the Altera FLash programmer can program an external flash that is CFI compliant. I assume that if I use such a device (one that is CFI compliant) then I simply add a common flash interface within the SOPC system and set my reset address to the correct address range within the CFI/external flash and on reset the boot loader will do the rest. But what hapenns if I want to use an external flash device that is not CFI compliant (e.g. a serial flash /SPI) ? How do I program it (it sounds like I will not be able to use the ALtera Flash Programmer ?) and how do I boot from it ? Do I have to create a customize component to do this work ? If yes, how and what - is there any documentation on this ? How do most people work with multi-processor designs ? What type of external flash devices do they use and how do they program them and boot from them ?
