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Honored Contributorboot NIOS from EPCS flash and use SDRAM to store instructions and data
Hi! In the qsys I have:
1. Clock Source 2. On-Chip Memory 3. Nios II Processor 4. System ID 5. JTAG UART 6. EPCS Serial Flash Controller 7. PIO 8. SDRAM Controller I want to use SDRAM (MT48LC4M32B2) to store instructions and data for NIOS application. In the NIOS II Processor properties reset vector is set to base address of EPCS controller. Exceptions vector is set to base address to SDRAM. In the NIOS EDS for Eclipce I can debug my application, it works. But in the NIOS flash programmer error occur: "Error: Error code: 4 for command: $SOPC_KIT_NIOS2/bin/nios2-flash-programmer "D:/Work/QuartusProjects/tests/test2/flash/test2_epcs_flash.flash" --base=0x2003800 --epcs --sidp=0x2004010 --id=0x0 --timestamp=1359654107 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program" What I did wrong? Thank you29 Replies
Altera_ForumThank you! A am already doing that)) I'll answer later, my computer is very slow, it take a lot of time to recompile the project
- Altera_Forum
Boot code is just code that copies data from the boot device (in this case the EPCS device) and main memory.
An ELF program (as output by ld) has 'program headers' (run objdump -p) that make it very simple to load. To get C code running on the nios you need asm instructions to set %sp and %gp and then jump to the C function (don't call it main()). I've never had to access EPCS type memory - but it can't be hard! - Altera_Forum
If in the Linker Script tab of the BSP Editor I set all of Linker Region Name to on-chip memory my system works and boot from EPCS after power on. If I set all of Linker Region Name to SDRAM it not works, but I can launche it and debug...I don't understand why
- Altera_Forum
Did you recompile and reflash the EPCS after changing the linker sections?
- Altera_Forum
Yes, I did
- Altera_Forum
I'm using the sections as you can see in the attached screenshot. The instruction master must connected to sdram in qsys.
But if you can debug code running from sdram it should connected already. Jens - Altera_Forum
Thank you for your reply! It connected. I use the follow configuration of my system (added pictures). Is it correct?
- Altera_Forum
At the moment I can not see a difference to my section mappings. I attached a part of my BSP settings where the sdram is referenced.
How do you verify in your onchip-ram based system the nios processor is booting correct from EPCS? - Altera_Forum
I mapped all sections to on-chip memory, rebuild project and from Flash Programmer write *.elf to EPCS. After that my system boot from EPCS, I can see it from Signal Tap Logic Analyzer. There is a PIO-out, which say me, that NIOS is working (and signals of two sgdma). When I mapped all of sections to SDRAM, this signal is always zero (and signals of sgdma too).
- Altera_Forum
Have you tried writing code that does a memory test of the SDRAM?
