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Altera_Forum's avatar
Altera_Forum
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12 years ago

Bidirection port (PIO) in uClinux

Hi all,

does somebody design and program, in which is using pio core in bidirection mode ?

I need to communicate between two FPGAs with one control bus (in output pio mode) and bidirection bus for address and data, but when i use program like this

------------

void write_sigp(unsigned long adresa,unsigned long hodnota)

{

printf("Zapisuji hodnotu na adresu 0x%x=0x%x.\n",adresa,hodnota);

// set output mode on io bus

outl(0xFFFFFFFF,IO_PIO_SMER+0x80000000);

//write address on io bus

outl(adresa,IO_PIO+0x80000000);

usleep(1);

// strobe address

outb(NONE-ASTB,OUTPUT_PIO+0x80000000);

usleep(1);

outb(NONE,OUTPUT_PIO+0x80000000);

usleep(1);

// write data on io bus

outl(hodnota,IO_PIO+0x80000000);

usleep(1);

// set /WR signal

outb(NONE-WR,OUTPUT_PIO+0x80000000);

usleep(1);

outb(NONE,OUTPUT_PIO+0x80000000);

// set input direction of io bus

outl(0x00000000,IO_PIO_SMER+0x80000000);

}

// reading from second fpga

unsigned long read_sigp(unsigned long adresa)

{ unsigned long out_data=0xffffffff;

// set output direction pio

outl(0xFFFFFFFF,IO_PIO_SMER+0x80000000);

// write address on io bus

outl(adresa,IO_PIO+0x80000000);

usleep(1);

// strobe addres

outb(NONE-ASTB,OUTPUT_PIO+0x80000000);

usleep(1);

outb(NONE,OUTPUT_PIO+0x80000000);

usleep(1);

// set input direction in io bus

outl(0x00000000,IO_PIO_SMER+0x80000000);

// set /RD signal

outb(NONE-RD,OUTPUT_PIO+0x80000000);

usleep(1);

// read value from io bus

out_data = inl(IO_PIO+0x80000000);

// reset /RD signal

outb(NONE,OUTPUT_PIO+0x80000000);

usleep(1);

printf("Nacitam hodnotu z adresy 0x%x=0x%x.\n",adresa,out_data);

return(out_data);

}

------------

IO_PIO_SMER = IO_PIO base address + 1

------------

nothing is setting in bidirection bus on their pins. In output pio bus is setting and reseting control signal right.

Or is neccessary to use some linux driver for use io bus ? Where, or how to set ?

(when i use only nios2 processor and c language, it works ok)

Thank you for your answer.

Jan Naceradsky, Czech Republic

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    IO_PIO_SMER = IO_PIO base address + 1

    --- Quote End ---

    You might want to try IO_PIO_SMER = IO_PIO base address + 4 instead. The hardware documentation usually talks about offsets for 32-bit registers, while the address used in software is in a 8-bit space. You need to jump 4 bytes to get to the next offset.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hmm, when i use offset + 4, the program after setting IO_PIO_SMER to 0xFFFFFFF is jamming :(.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    1. you may do PIO directly in uClinux without device driver. you already know about uncache acccess with 0x80000000 adress mask. But you should know that you are working in user space, which may be sleeped and you can not control the timing.

    2. the address map is count by 4 bytes word. so it should be +4 instead of +1. Please list your address map. You may set the uncache mask in your address rather than do it in your in()/out().

    3. Please stick to outl() and inl(). there is no address translation in altera pio core. please do not use outb()/inb().

    4. Please watch out for bus contention, ie, two output pins short together. The fpga chip will fail in this case. Please design our protocol carefully to avoid contention.

    5. Please clarify why you use NONE-WR etc, they are not good value or symbol name.

    Regards,

    Hippo
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    And how can I uncache mask set ?

    In my program i use ?

    -----

    // control signals /CB0=RD/CB1=WR/CB2=ASTB

    # define RD 1

    # define WR 2

    # define ASTB 4

    # define NONE 0xFF

    // obousmerna 32-bitova sbernice pro data i adresu

    # define IO_PIO 0x020030C0

    ------

    Or i will must use button port and led port with linux driver ? Some linux driver for general IO bus isn´t ?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I think this is mostly interface design problem, not about Linux.

    Please show all your PIO address map.

    For uncache mask, I mean you can use# define IO_PIO 0x820030C0

    For protocol, I mean you should initialize the control port data and data port direction at the beginning. And study the handshake signal carefully to avoid contention. Do you understand what I mean about bus contention? You may try signle step and use oscilliscope to check the signal level.

    If your control signals are active low, you can add invertor to output pins at the top level design. You may assign power on value, too.

    - Hippo
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    in last week i changed the port from bidirection on output port and use rotation bits from 0.bit to 31.bit and when i send "0" to 18.bit and 20.bit,

    //-------------------------------MAIN-------------------------------------------

    int main(int argc, char *argv[])

    { unsigned long l,ch;

    int i;

    printf("--------------- Start program. ------------\n");

    for(;;)

    { l = 1;

    for(i=0;i<32;i++)

    { ch=0xffffffff - l;

    printf("Write %x.\n",ch);

    outl(ch,IO_PIO+0x80000000);

    usleep(2);

    outl(0xffffffff,IO_PIO+0x80000000);

    sleep(2);

    l = l*2;

    }

    }

    }

    -----------

    the system is halted (none possible to use command line in nios2-terminal, everything stop. I disconnected pins on the board from all external "world", but it "works" same. I dont understand why ?

    I use EP3C25Q240C8N and use epcs controller, uart, jtag uart, sd card (SPI 3-wire serial), sdram, igor mac and every peripheral device look ok....

    Jan
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    It looks like that some of the output pins are shorted on your board.

    - Hippo
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Are you sure that your IO_PIO define is the correct address? Sometimes when you regenerate your SOPC/QSYS system, base addresses of some components can change.

    Is the PIO device getting its clock?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Finally I found that when i write "0" to ad[19] to pin88 of EP3C25Q240, system halted, so i discovered, that this pin can be use for sdram controller. I use sdram controller, but not this pin. Although it is strange, i changed the pin location from pin88 to pin126 and now it works in bidirection pio mode, too (communicate with second fpga).

    In second, you are true, I had to write IO_PIO_SMER = IO_PIO base address + 4.

    I dont understand why is problem when i write 0 to pin 88, but now it works.

    Thank you for your advices.

    Jan