Also Problems with Hello World

Simple answer: This error message occurs when the hardware image which has been programmed into the board doesn't match the one being used to generate the software for your system.

Simple solution: Make sure that you reprogram the board with the current hardware image being used to generate the software for the system. To accomplish this goal, recompile your Quartus II project and download the generated SOF file to the board.

Just remember that any changes you make to your Nios II system in SOPC Builder will cause the Nios II IDE to present this error again.

Additionally, if you are positive that you haven't changed the system, you can by-pass the check of the system ID in the Nios II IDE. To do this, in the Nios II IDE select "Run -> Debug..." and pick your download configuration. In the first tab, uncheck the "Validate Nios II system ID before software download" item. This will prevent the Nios II IDE from checking the system hardware for the system ID.

Hope this helps,

Chris

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originally posted by niostwo@Jun 12 2006, 03:21 AM

if i try to run the example project hello world i got the following error? i have also recompiled my system but it doesnt help? has anybody an idea why this can happen?

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reading system id at address 0x00810828: does not match

id value does not match: read 0xe0800b15; expected 0xbb381db2

timestamp value does not match: image on board is older than expected

read timestamp 5:42:34 1970/01/05; expected 11:53:31 2006/04/21

the software you are downloading may not run on the system which is currently

configured into the device. please download the correct sof or recompile.

restarting target processor

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If you are using a Nios Development board make sure you have one of the following:

The reconfig request pin (bidirectional pin) --> see the full featured design

or

Under the device options make sure the unused I/O option is set to "input tri-state"

The reason for this is that there is a signal from the FPGA going to the CPLD on the board used to tell the CPLD to re-program a new imagine into the FPGA. This is an active low signal, and by default Quartus II sets unused I/O to ground (so you might be programming the FPGA via JTAG only to have the CPLD reprogram the FPGA immediately after).