Also Problems with Hello World

If you are using a Nios Development board make sure you have one of the following:

The reconfig request pin (bidirectional pin) --> see the full featured design

or

Under the device options make sure the unused I/O option is set to "input tri-state"

The reason for this is that there is a signal from the FPGA going to the CPLD on the board used to tell the CPLD to re-program a new imagine into the FPGA. This is an active low signal, and by default Quartus II sets unused I/O to ground (so you might be programming the FPGA via JTAG only to have the CPLD reprogram the FPGA immediately after).