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Honored Contributor
Honored ContributorAddressing in hex file
Hello,
I currently design a system with SOPC based on the Nios II processor. I checked the hex file generated by the Nios II IDE after compilation. At the beginning I have the following : :020000020000FC Which means that the address will not be on 16 bits but on 20 bits (four 0 are added at the end) (cf http://en.wikipedia.org/wiki/intel_hex) (http://en.wikipedia.org/wiki/intel_hex%29). --- Quote Start --- 02, extended segment address record, segment-base address. Used when 16 bits are not enough, identical to 80x86 real mode addressing. The address specified by the 02 record is multiplied by 16 (shifted 4 bits left) and added to the subsequent 00 record addresses. This allows addressing of up to a megabyte of address space. The address field of this record has to be 0000, the byte count is 02 (the segment is 16-bit). The least significant hex digit of the segment address is always 0. --- Quote End --- The next lines of the hex file are : :20000000008400141001483A10BFF80400BFFD1600400034087008140800683A0000000066 :20000800008400141000003310BFF80400BFFD1606C00074DEC0001406800074D690B1144F :200010000080003410B0B41400C0003418F0B41410C00326100000151080010410FFFD36DB :20001800000C0880000C16C0003FFF06DEFFFF04DF000015D839883A0005883ADF000017AA ... The first address is 0x00000, the second is 0x00080, the third 0x00100, ..., so there are 128 addresses between each address . However, there are only 32 bytes of data on each line. So I don't understand very well the organisation, and what are the data between addresses 0x00020 and 0x00080 for example. Does someone have a explanation for that ? Thanks in advance. Jérôme16 Replies
Altera_Foruma byte is a byte and has 8 bit
if you address bytewide then you get access to 8 bit per access only if you want to access a word (16bit) then your address must be aglined to 16bit boundaries so possible adr is 0x0 0x1 0x2 (from 16bit point of view) what is 0x0 0x2 0x4 in bytewide view same in 32bit. the lsb of the 32bit data is the lsb of 8bit data but the msb of your 32bit is the msb of the 4. data byte think of an array and let the contect be {0,1,2,3,4,5,6,7,8,9,....} accessing this memory bytewide you will see at adr[0] 0x0 adr[1] 0x1 adr[2] 0x2 adr[3] 0x3 adr[4] 0x4 but now in 16 bit access mode adr[0] 0x0100 adr[2] 0x0302 adr[4] 0x0504 and in 32 bit adr[0] 0x03020100 adr[4] 0x07060504 if you write down the possible addresses in binary maybe this helps you 8 bit 00000 00001 00010 00011 00100 00101 16 bit 00000 00010 00100 00110 01000 32 bit 00000 00100 01000 01100 10000 showing only the lowest 5 adr bits- Altera_Forum
Argh. We don't arrive to understand each other. Maybe is because my question has no sense when we know how it is done physically.
My idea of a memory (imagine it as a town) is, we have an address bus that permit to access a memory element (imagine it is as a building). The size of the address bus will simply indicate how many memory element we can access (bus of N bits => access to 2^N elements (2^N building in the town)). You have a first type of memory where the size of an element is 8 bits (your building has 8 floors). So the data bus is 8-bit length. Why can we not imagine a memory where the size of an element is 32 bits (your building has 32 floors), or 24 or even 15 if we want ? I hope this metaphor will help to be understood. - Altera_Forum
the addressbus is adressing bytes if you look at it with all bits.
nios is normaly looking at your memory from a 32bit view thus it doesn't know the lower 2 bits if you access parts of 32 bit = 4 byte within a 4 byte alignment then nios / avalon uses the byteenables to tell the switchfabric what part of the complete 32bit is accessed. i understand what you want to ask, but the thing is a 8 bit dus width master has N addresbits, an 16bit master has N-1 and a 32bit Master has N-2 bit wide address bus. all of them have the same addressspan in bytes. if your memory is 1MByte (8bit) then it is 0,5MWord (16Bit) or 0,25MLongWords (32bit) they all have the same complete memory size, but different bit width. - Altera_Forum
This way of working is not the one of the Nios only because I think it is the same for processor inside PC for example (and probably other processors).
But, would it not be more simple if the depth of the memory was the same than the depth of the bus ? - Altera_Forum
from nios side of view there is no difference if the target memory is 8 16 or 32 bit wide.
the translation is handled by the avalon switch fabric. even if you copy from an 8 bit target to a 16 bit target. a 32 bit master is capable of fetching 4x the data as an 8 bit master in 1 clock cycle. thus does not need to address the memory 4 times. they other way round, if you connect an external 8 bit memory and an 32 bit memory to your fpga, then you must connect the 8bit slaves lowest addressignal to the fpga lowest addressignal lets call this call tristate_bus_a[..] where the lowest signal is tristate_bus_a[0] and is connected to 8bitmemory_a[0]. but the 32bit memory ist connected differently 32bitmemory_a[0] goes to tristate_bus_a[2] - Altera_Forum
Ok. Thanks for the explanations.
