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Altera_Forum's avatar
Altera_Forum
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21 years ago

Address alignment

1.

There are IORD,IOWR routines. It is right to IORD_32DIRECT("*000 *004 *008 *00C")! Then is it right to IORD_32DIRECT("*001 *005 *009 *00C...") or IORD_8DIRECT("*001 *002 *003 *004...") when accesses the tristate slaves?? And while accesses the "normal" slave, such as registers in UART, which address should we keep in mind in IORD/IOWR? Master or slave address?

(reference: I look up quartusii_handbook(may 2005) p1302 (http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf) andavalon interface specification(april 2005) p67 p88 (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) about "Address alignment". As NiosII is 32-bit CPU, so the master address is always "*000 *004 *008 *00C" . However the "the tristate slave" is always byte-address("*000 *001 *002 *003...")

In another words, when there are some registers in a tristate slave comopent(8 bit ), what's address in IORD/IOWR? IS it *001 *002 *003 *004... or *000 *004 *008 *00C? Maybe it is a common sense , but it is confuse me.

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2.

By the way, when SDRAM shares the tristate bus, the addresses(A11-A0) of SDRAM(32-bit data width) should connect to (A13-A2) of the tristate bus?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    mountain8848,

    1.)

    your hw-access depends on the type of interface: if it is a register-type interface you always have 32-bit aligned ports even you've defined an 8-bit port. So the lower two address bits are ignored, direct accesses to 0,1,2,3 are equivalent.

    Only if your interface is a memory-type interface, accesses are aligned in the 'dynamic bus sizing' mode, where bytes a byte-aligned, words are word-aligned and Dwords are Dword-aligned.

    2.)

    when using Alteras 'SDRAM controller' SDRAM an Avalon-Tri-State bus have to be connected 1:1 (A0 to A0, A1 to A1, ..) . A 16-Bit device's signal LDQM has to be connected to byteenable[0], UDQM to byteenable[1] (I've connected Mitels MT48LC8M16A2 in this way).

    Mike
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Thank you, Mike.

    1)

    When we add a User component as 8-bit data, 3-bit address, register-type like PWM-module, SOPC builder will map the component *00--*1F. Why not *00--*08? After your explaination, because the 32-bit-width and register-type, it should be "multiply" by 4. But comes another question, the A2, A1, A0 of Components is "automaticlly" connected to A4, A3, A2 of "Master" in these situation??

    2)

    Take SRAM(memory-type , tristate slave) in Nios Kit as an example, we connect 19..2 from SOPC builder to 17..0 of the SRAM, and byteenable[3..0] connects proper signals.

    (assume 0x1 is in the map of SRAM)

    IORD_32direct(0x1) ==>we get the data of 0x00,0x01,0x02,0x04 of SRAM

    IORD_16direct(0x1) ==>we get the data of 0x00,0x01 of SRAM

    IORD_8direct(0x1) ==>we get the data of 0x01 of SRAM

    Isn't it? And in my opinion, byte and word are selected by "byteeanble" when accessing SRAM as A1,A0 are ignored, while accessing ext_flash, it is select by A1,A0 actually. I used to think A1, A0 were always ignored in 32-bit system.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    mountain8848,

    1)

    Registers are internally 32-Bits wide, but only the lower 8 bits are used in your case. With A2-A0 you have 8 locations that spans an area of 8 x 4Bytes = 32Bytes in the memory map (0x0 - 0x1F). Consecutive writes to these locations can be done as 

    *(alt_u8 *)(BASE + 0) = 1;
*(alt_u8 *)(BASE + 4) = 2;
*(alt_u8 *)(BASE + 8) = 3;
or
*(alt_u8 *)(BASE + 3) = 1;
*(alt_u8 *)(BASE + 7) = 2;
*(alt_u8 *)(BASE + 11) = 3;
or
*(alt_u32 *)(BASE + 0) = 1;
*(alt_u32 *)(BASE + 4) = 2;
*(alt_u32 *)(BASE + 8) = 3;

    which will have the same results. The address A[4..2] of an Avalon-Master are mapped to A[2..0] of the register slave, as you supposed.

    2)

    The difference between SRAM and SDRAM connected to TRi-State-Avalon is, that there is a special SDRAM-controller, managing different row- and column- addresses. During a SDRAM-access, these address lines are multiplexed with absolute Avalon addresses. So it depends on the actual access if row-addresses, column-addresses or absolute addresses are present on these lines. In this special case A0 means A0! (I also had to correct this in my design).

    Mike