Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAddress alignment
1. There are IORD,IOWR routines. It is right to IORD_32DIRECT("*000 *004 *008 *00C")! Then is it right to IORD_32DIRECT("*001 *005 *009 *00C...") or IORD_8DIRECT("*001 *002 *003 *004...") when a...
Altera_ForumHonored Contributor
Honored ContributorThank you, Mike.
1) When we add a User component as 8-bit data, 3-bit address, register-type like PWM-module, SOPC builder will map the component *00--*1F. Why not *00--*08? After your explaination, because the 32-bit-width and register-type, it should be "multiply" by 4. But comes another question, the A2, A1, A0 of Components is "automaticlly" connected to A4, A3, A2 of "Master" in these situation?? 2) Take SRAM(memory-type , tristate slave) in Nios Kit as an example, we connect 19..2 from SOPC builder to 17..0 of the SRAM, and byteenable[3..0] connects proper signals. (assume 0x1 is in the map of SRAM) IORD_32direct(0x1) ==>we get the data of 0x00,0x01,0x02,0x04 of SRAM IORD_16direct(0x1) ==>we get the data of 0x00,0x01 of SRAM IORD_8direct(0x1) ==>we get the data of 0x01 of SRAM Isn't it? And in my opinion, byte and word are selected by "byteeanble" when accessing SRAM as A1,A0 are ignored, while accessing ext_flash, it is select by A1,A0 actually. I used to think A1, A0 were always ignored in 32-bit system.
