Address alignment

mountain8848,

1)

Registers are internally 32-Bits wide, but only the lower 8 bits are used in your case. With A2-A0 you have 8 locations that spans an area of 8 x 4Bytes = 32Bytes in the memory map (0x0 - 0x1F). Consecutive writes to these locations can be done as

*(alt_u8 *)(BASE + 0) = 1;
*(alt_u8 *)(BASE + 4) = 2;
*(alt_u8 *)(BASE + 8) = 3;
or
*(alt_u8 *)(BASE + 3) = 1;
*(alt_u8 *)(BASE + 7) = 2;
*(alt_u8 *)(BASE + 11) = 3;
or
*(alt_u32 *)(BASE + 0) = 1;
*(alt_u32 *)(BASE + 4) = 2;
*(alt_u32 *)(BASE + 8) = 3;

which will have the same results. The address A[4..2] of an Avalon-Master are mapped to A[2..0] of the register slave, as you supposed.

2)

The difference between SRAM and SDRAM connected to TRi-State-Avalon is, that there is a special SDRAM-controller, managing different row- and column- addresses. During a SDRAM-access, these address lines are multiplexed with absolute Avalon addresses. So it depends on the actual access if row-addresses, column-addresses or absolute addresses are present on these lines. In this special case A0 means A0! (I also had to correct this in my design).

Mike