Address alignment

mountain8848,

1.)

your hw-access depends on the type of interface: if it is a register-type interface you always have 32-bit aligned ports even you've defined an 8-bit port. So the lower two address bits are ignored, direct accesses to 0,1,2,3 are equivalent.

Only if your interface is a memory-type interface, accesses are aligned in the 'dynamic bus sizing' mode, where bytes a byte-aligned, words are word-aligned and Dwords are Dword-aligned.

2.)

when using Alteras 'SDRAM controller' SDRAM an Avalon-Tri-State bus have to be connected 1:1 (A0 to A0, A1 to A1, ..) . A 16-Bit device's signal LDQM has to be connected to byteenable[0], UDQM to byteenable[1] (I've connected Mitels MT48LC8M16A2 in this way).

Mike