Achieving higher performance?

Possibly you had problems with the internal memory regions, using a few less M9K blocks might help.

I think a pipeline bridge (or even a non-pipeline bridge) can be used to:

1) reduce the number of complex slave arbitors by putting multiple slaves behind the bridge.

2) allow you to run some slaves at a lower clock frequency.

Both will increase the time taken to access the bridged slaves.

It ought to be possible to use the timing tools to work out the critical path. But I'm a software engineer... :-)

Yes i agree with you.

How can i use pipeline bridgers?

I am also a software engineer :P

If you with to run at 100 MHz, set the clock constrain in the .SDC to 10 ns and then synthesize the design again.

Assuming it will fail to meet that constrain, then one option is to change the synthesis and fitting settings for speed and try again.

If it still fails, you need to track down the critical paths.

If you find the critical path is related to a slave, you can consider using a dual clock bridge to run that clock at a lower frequency.

If you find the critical path is related to the Avalon fabric itself, then:

a) do you have unnecessary master-slave connections in your bus?

b) consider using pipeline or dual clock bridges to reduce the complexity.

In order to use bridged, you need to place a bridge in your SOPC.

The bridge will have a master and a slave port.

Connect your masters to the bridge's slave port.

Connect the bridge's master port to the slaves you want to place under the bridge.

Oh, important:

You need to ajust not only the clock period in the .SDC but you also need to make sure the clock frequency settings are correct in any components that have them (ie, PLLs, SDRAM controller, etc).

Yes.

It may not be the best performing option, though.

But that you'll have to go by try and error.

Humm linux stoped working after i inserted a pipeline bridge but i will do other tests to see how far i can go..

And when is it indicated to use a pipeline bridge?

Couldn't make Linux work using a pipeline bridger nor a clock crossing bridge.

Taking a look at the Quartus II report my FMax raised from 110 to 115 MHZ using a clock crossing bridge between my CPU & SDRAM and my Timers/uart/sysid/pios. Nothing relevant.