About the SDRAM clock delay compensate.

After checking the development board(cyclone) schematic, I found that the Extport of the connector_pll---pld_clockout drives a clock buffer chip(PI49FCT3805) and the PI49FCT3805's output(pld_clkfb) feeds the sdram_pll. This clock signal then be shifted -72degree to drive the sdram(sdram_clk).

Why?

In my opinion, there are multi devices on the development board use the clk signal of the Nios CPU, the connector_pll just does this work----- export the Nios clk signal to the clock buffer(PI49FCT3805). Devices like the config_controller CPLD will use the buffered clock. One of the buffered clock signal then goes into the FPGA to feed the sdram_pll because the cyclone pll cannot be fed by a internal clock signal, i.e it's input must comes outside. After shifting some degree, the buffered signal then goes out of the FPGA to drive the SDRAM. Maybe the -72 degree is the compenstation of the round-trip of the clk.

Am I right?

crystal---->connector_pll----->PI49FCT3805(buffer)----->sdram_pll----->sdram

Remy,

Your analysis is correct. On Stratix/S-II we do not have this restriction and you'll see that we use one PLL, with a zero-shift system clock and shifted SDRAM clock output.

Your question about why: This has been discussed before on this forum and on comp.arch.fpga.. if you search for 'sdram pll' or something similar I think you'll find the details.

You should note that the phase shift is *not* derived in degrees phase; its measured in nanoseconds and put into the PLL wizard which then calculates the phase shift for your desired clock speed. The shift is a constant time per board design, varying on trace lengths to SDRAM.