About the SDRAM clock delay compensate.

Remy,

Your analysis is correct. On Stratix/S-II we do not have this restriction and you'll see that we use one PLL, with a zero-shift system clock and shifted SDRAM clock output.

Your question about why: This has been discussed before on this forum and on comp.arch.fpga.. if you search for 'sdram pll' or something similar I think you'll find the details.

You should note that the phase shift is *not* derived in degrees phase; its measured in nanoseconds and put into the PLL wizard which then calculates the phase shift for your desired clock speed. The shift is a constant time per board design, varying on trace lengths to SDRAM.