About the SDRAM clock delay compensate.

After checking the development board(cyclone) schematic, I found that the Extport of the connector_pll---pld_clockout drives a clock buffer chip(PI49FCT3805) and the PI49FCT3805's output(pld_clkfb) feeds the sdram_pll. This clock signal then be shifted -72degree to drive the sdram(sdram_clk).

Why?

In my opinion, there are multi devices on the development board use the clk signal of the Nios CPU, the connector_pll just does this work----- export the Nios clk signal to the clock buffer(PI49FCT3805). Devices like the config_controller CPLD will use the buffered clock. One of the buffered clock signal then goes into the FPGA to feed the sdram_pll because the cyclone pll cannot be fed by a internal clock signal, i.e it's input must comes outside. After shifting some degree, the buffered signal then goes out of the FPGA to drive the SDRAM. Maybe the -72 degree is the compenstation of the round-trip of the clk.

Am I right?

crystal---->connector_pll----->PI49FCT3805(buffer)----->sdram_pll----->sdram