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Altera_Forum's avatar
Altera_Forum
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19 years ago

16 bit extrenal SRAM

Dear all,

I have made an NIOS 2 processor which has access to an 16b SRAM.

The SOPC tri-state bridge address (total width = 19) [A18 downto A1] is connected

to the SRAM address (total width = 18) [A17 to A0].

I have written a write/read loop accessing the SRAM

ex.

for(i=0;i<100;i++)

{

unsigned int * sram = (int *)(SRAM_BASE_ADDRESS + i);

*sram = i;

}

When I read out the data again, I get following results

3,3,3,3,7,7,7,7,11,11,11,11,... instead of 0,1,2,3,4,5,6,....

For some reason, the address bits A0 and A1 are ignored .... Have anyone an idea where the problem is situated

Kind

regards

Karel

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Hi,

    Are you using the stock SRAM component, provided by Altera? It will only work with the flavor of SRAMs found on Nios Dev. Kits.... i.e.: 32 bits wide

    If you&#39;ve already designed your own custom SRAM interface, then ignore this post. If not, then you need to either create yourself a component using the component editor (builder??) or modify the existing component to suite your needs. I would recommend the latter, but it depends on your comfort level with editing the class.ptf file...

    Cheers, and Good luck, whatever you decide.

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    I have made alreay my own 16 bit sram component.

    So, that isn&#39;t the problem .... maybe it has something to do

    with dynamic addressing?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Yeah, all memory interfaces are required to support dynamic addressing.

    Are you connecting byte enables to the SRAM? That would be what I would expect for a 16 bit interface. Take a look at the 32-bit SRAM in the Altera designs and you&#39;ll see 4 BEs, 2 going to each 16 bit SRAM chip.

    Cheers,

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Slacker,

    Yes, the byte-enables are connected to my SRAM device....

    I think I have found the reason why writing to offsets 0,1,2 and 3 gives the same result.

    In the avalon memory map interface document, you can find following table

    for dynamic addressing:

    Table 7: Dynamic Bus Sizing Master-to-Slave Address mapping

    32-Bit Master Data

    Master Address When Accessing a 16-Bit Slave Port

    0x00 OFFSET[1]15..0:OFFSET[0]15..0

    0x04 OFFSET[3]15..0:OFFSET[2]15..0

    0x08 OFFSET[5]15..0:OFFSET[4]15..0

    0x0C OFFSET[7]15..0:OFFSET[6]15..0

    So, this is also what I see in my results ... A write to addess 0x00 results in a two 16b write cycle, namely to offset slave 0 and offset 1.

    When I write to 0x01,0x02 or 0x03, I think this has the same result as writing to 0x00 ... thats why I get always value 3 back when reading out 0x00,0x01,0x02 and 0x03 ... (see for loop above) ....

    So, I think I always should give an offset incremented by four when writing to the 16b SRAM by means of a 32b master (avalon tri-state)

    Regards

    Karel