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Altera_Forum
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19 years ago

16 bit extrenal SRAM

Dear all, I have made an NIOS 2 processor which has access to an 16b SRAM. The SOPC tri-state bridge address (total width = 19) [A18 downto A1] is connected to the SRAM address (total width...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Slacker,

Yes, the byte-enables are connected to my SRAM device....

I think I have found the reason why writing to offsets 0,1,2 and 3 gives the same result.

In the avalon memory map interface document, you can find following table

for dynamic addressing:

Table 7: Dynamic Bus Sizing Master-to-Slave Address mapping

32-Bit Master Data

Master Address When Accessing a 16-Bit Slave Port

0x00 OFFSET[1]15..0:OFFSET[0]15..0

0x04 OFFSET[3]15..0:OFFSET[2]15..0

0x08 OFFSET[5]15..0:OFFSET[4]15..0

0x0C OFFSET[7]15..0:OFFSET[6]15..0

So, this is also what I see in my results ... A write to addess 0x00 results in a two 16b write cycle, namely to offset slave 0 and offset 1.

When I write to 0x01,0x02 or 0x03, I think this has the same result as writing to 0x00 ... thats why I get always value 3 back when reading out 0x00,0x01,0x02 and 0x03 ... (see for loop above) ....

So, I think I always should give an offset incremented by four when writing to the 16b SRAM by means of a 32b master (avalon tri-state)

Regards

Karel