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Altera_Forum
Honored Contributor
Honored Contributor16 bit extrenal SRAM
Dear all, I have made an NIOS 2 processor which has access to an 16b SRAM. The SOPC tri-state bridge address (total width = 19) [A18 downto A1] is connected to the SRAM address (total width...
Altera_ForumHonored Contributor
Honored ContributorYeah, all memory interfaces are required to support dynamic addressing.
Are you connecting byte enables to the SRAM? That would be what I would expect for a 16 bit interface. Take a look at the 32-bit SRAM in the Altera designs and you'll see 4 BEs, 2 going to each 16 bit SRAM chip. Cheers, - slacker
